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고 전력 DMOSFET 응용을 위한 트렌치 게이트 형성에 관한 연구
박훈수,구진근,이영기 한국전기전자재료학회 2004 전기전자재료학회논문지 Vol.17 No.7
In this study, the etched trench properties including cross-sectional profile, surface roughness, and crystalline defects were investigated depending on the various silicon etching and additive gases, For the case of HBr$He-O_2SiF_4$ trench etching gas mixtures, the excellent trench profile and minimum defects in the silicon trench were achieved. Due to the residual oxide film grown by the additive oxygen gas, which acts as a protective layer during trench etching, the undercut and defects generation in the trench were suppressed. To improve the electrical characteristics of trench gate, the hydrogen annealing process after trench etching was also adopted. Through the hydrogen annealing, the trench corners might be rounded by the silicon atomic migration at the trench corners having high potential. The rounded trench corner can afford to reduce the gate electric field and grow a uniform gate oxide. As a result, dielectric strength and TDDB characteristics of the hydrogen annealed trench gate oxide were remarkably increased compared to the non-hydrogen annealed one.
Electrical Characteristics of a High-voltage P-channel LDMOSFET Utilizing SOI Technology
박훈수,Jin-Gun Koo,Sang-Gi Kim,Jin-Young Kang 한국물리학회 2009 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.55 No.3
In this paper, the electrical characteristics of a high-voltage p-channel LDMOSFET (lateral double-diffused metal oxide silicon field effect transistor) fabricated by using SOI technology are presented. The breakdown voltage characteristic of the p-LDMOS device, which depended on the drift layer length, was evaluated in detail. In order to optimize the electrical performance of a p-LDMOSFT having a thick gate oxide, we analyzed the influences of the p-drift junction formation and the drain and the gate field plates on the on- and off-state breakdown voltages. In this paper, the electrical characteristics of a high-voltage p-channel LDMOSFET (lateral double-diffused metal oxide silicon field effect transistor) fabricated by using SOI technology are presented. The breakdown voltage characteristic of the p-LDMOS device, which depended on the drift layer length, was evaluated in detail. In order to optimize the electrical performance of a p-LDMOSFT having a thick gate oxide, we analyzed the influences of the p-drift junction formation and the drain and the gate field plates on the on- and off-state breakdown voltages.
Pt-nSi쇼트키 접촉의 유효 장벽높이 감소에 관한 연구
박훈수,김봉열 한국전기전자재료학회 1989 電氣電子材料學會誌 Vol.2 No.1
낮은 에너지(60KeV) 비소 이온주입으로 고종도의 얇은 표면층을 형성시켜 Pt-nSi 쇼트키 다이오드의 유효 장벽높이를 감소시켰다. 역방향 특성을 크게 저하시키지 않고 순방향 임계전압을 400mV에서 200mV로 낮추는데 필요한 이온주입량은 얇은 산화막(215.angs.)이 존재하는 상태에서 비소 이온주입을 한 경우는 9.0*$10^{12}$$cm^{-2}$이고, 산화막이 없는 상태에서 이온주입한 경우는 5.1*$10^{12}$$cm^{-2}$이었다. 이온주입후 열처리 조건은 900.deg.C에서 30분간 N$_{2}$분위기에서 행하였으며 얇은 산화막을 통한 이온주입으로 다이오드의 역방향 특성을 개선하였다.
자기 정열과 수소 어닐링 기술을 이용한 고밀도 트랜치 게이트 전력 DMOSFET의 전기적 특성 분석
박훈수,김종대,김상기,이영기 한국전기전자재료학회 2003 전기전자재료학회논문지 Vol.16 No.10
In this study, a new simplified technology for fabricating high density trench gate DMOSFETs using only three mask layers and TEOS/nitride spacer is proposed. Due to the reduced masking steps and self-aligned process, this technique can afford to fabricate DMOSFETs with high cell density up to 100 Mcell/inch$^2$ and cost-effective production. The resulting unit cell pitch was 2.3∼2.4${\mu}$m. The fabricated device exhibited a excellent specific on-resistance characteristic of 0.36m$\Omega$. cm$^2$ with a breakdown voltage of 42V. Moreover, time to breakdown of gate oxide was remarkably increased by the hydrogen annealing after trench etching.