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공명국,김도우,Gong, Myeong-Kook,Kim, Do-Woo 한국전기전자재료학회 2008 전기전자재료학회논문지 Vol.21 No.1
A resistor network model for the horizontal AlInGaN LED was investigated, The parameters of the proposed model are extracted from the test dies and $350{\mu}m$ LED, The center of the P-area is the optimal position of a P-electrode by the simulation using the model. Also the optimal chip size of the LED for the new target current was investigated, Comparing the simulation and fabrication result, the errors for the forward voltage and the light power are average 0,02 V, 8 % respectively, So the proposed resistor network model with the linear forward voltage approximation and the exponential light power model are useful in the simulation for the horizontal AlInGaN LED.
김도우,공명국,왕진석 대한전기학회 2006 전기학회논문지C Vol.55 No.4(C)
- This paper presents an ASER (Accelerated Soft Error Rate) integral model. The model is based on the facts that the generated EHP's(electron hole pairs) are diminished after some residual range of the incident alpha particle, where residual range is a function of the incident angle and the capping layer thickness over the semiconductor junction. The ASER is influenced by the flux of the alpha particles, the junction area ratio, the alpha particle incident angle when the critical charge is same as the collected charge, and the sizes of the alpha source and the chip.The model was examined with 8M static RAM samples. The measured ASER data showed good agreement with the calculated values using the model. The ASER decreased exponentially with respect to the operational voltage. As the capping layer thickness increases up to 16㎛, the ASER increases, and after that thickness, the ASER decreases. The ASER increased as the depth of BNW increased from 0㎛ to 4㎛. and then saturated. The ASER decreased as the node capacitance increased from 2fF to 5fF.
김도우,공명국,왕진석 대한전기학회 2006 전기학회논문지C Vol.55 No.3(C)
- We investigated accelerated soft error rate(ASER) in 8M static random access memory(SRAM) cells. The effects on ASER by well structure, operational voltage, and cell transistor threshold voltage are examined. The ASER decreased exponentially with respect to operational voltage. The chips with buried nwell1 layer showed lower ASER than those either with normal well structure or with buried nwell1 + buried pwell structure. The ASER decreased as the ion implantation energy onto buried nwell1 changed from 1.5 MeV to 1.0 MeV. The lower viscosity of the capping layer also revealed lower ASER value. The decrease in the threshold voltage of driver or load transistor in SRAM cells caused the increase in the transistor on-current, resulting in lower ASER value. We confirmed that in order to obtain low ASER SRAM cells, it is necessary to use the buried nwell1 structure scheme and to fabricate the cell transistors with low threshold voltage and high on-current.
김도우,공다영,공명국,Kim, Dowoo,Gong, Dayeong,Gong, Myeongkook 한국전기전자재료학회 2013 전기전자재료학회논문지 Vol.26 No.7
An optical model is proposed in the white LED using phosphor and LED chip. In this paper a new model that describes the absorption rate and quantum efficiency with increasing the mixing ratio of phosphor in silicone, and the allotment of the phosphor absorption optical power in the several phosphor mixing in the silicone. Single phosphor in silicone from the optical measurement data before and after molding, the solution to get the blue optical power and the phosphor emission optical power is proposed. By these solution the absorption rate and the quantum efficiency was obtained. The model with single phosphor mixing in the silicone the validity was confirmed.