Design of a High Performance Patch Antenna for GPS Communication Systems

Sotoudeh Hamedi-Hagh,Joseph Chung,Sooseok Oh,Ju-Ung Jo,Noh-Joon Park,Dae-Hee Park 대한전기학회 2009 Journal of Electrical Engineering & Technology Vol.4 No.2

This paper presents the design of a patch antenna for GPS portable devices. The antenna is designed to operate at L1 band on an FR4 PCB with a thickness of 1.6㎜, a dielectric constant of 3.8 and two metallization layers. The antenna has a dimension of 49㎜×36㎜ and operates at 1.5754㎓ with a return loss of |-36|㏈ and a measured bandwidth of 250㎒.

Applications of Nanowire Transistors for Driving Nanowire LEDs

Sotoudeh Hamedi-Hagh,Dae-Hee Park 한국전기전자재료학회 2012 Transactions on Electrical and Electronic Material Vol.13 No.2

Operation of liquid crystal displays (LCDs) can be improved by monolithic integration of the pixel transistors with light emitting diodes (LEDs) on a single substrate. Conventional LCDs make use of filters to control the backlighting which reduces the overall efficiency. These LCDs also utilize LEDs in series which impose failure and they require high voltage for operation with a power factor correction. The screen of small hand-held devices can operate from moderate brightness. Therefore, III-V nanowires that are grown along with transistors over Silicon substrates can be utilized. Control of nanowire LEDs with nanowire transistors will significantly lower the cost, increase the efficiency, improve the manufacturing yield and simplify the structure of the small displays that are used in portable devices. The steps to grow nanowires on Silicon substrates are described. The vertical n-type and p-type nanowire transistors with surrounding gate structures are characterized. While biased at 0.5 V, nanowire transistors with minimum radius or channel width have an OFF current which is less than 1pA, an ON current more than 1 μA, a total delay less than 10 ps and a transconductance gain of more than 10 μA/V. The low power and fast switching characteristics of the nanowire transistor make them an ideal choice for the realization of future displays of portable devices with long battery lifetime.

Design of Next Generation Amplifiers Using Nanowire FETs

Sotoudeh Hamedi-Hagh,Sooseok Oh,Ahmet Bindal,Dae-Hee Park 대한전기학회 2008 Journal of Electrical Engineering & Technology Vol.3 No.4

Vertical nanowire SGFETs (Surrounding Gate Field Effect Transistors) provide full gate control over the channel to eliminate short channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10㎚ channel length and a 2㎚ channel radius. The amplifier dissipates 5㎼ power and provides 5㎔ bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5V, and a distortion better than 3% from a 1.8V power supply and a 20aF capacitive load. The 2nd and 3rd order harmonic distortions of the amplifier are -40㏈m and -52㏈m, respectively, and the 3rd order intermodulation is -24㏈m for a two-tone input signal with 10㎷ amplitude and 10㎓ frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high speed analog and VLSI technologies.

Design of UHF CMOS Front-ends for Near-field Communications

Sotoudeh Hamedi-Hagh,Maryam Tabesh,Sooseok Oh,Noh-Joon Park,Dae-Hee Park 대한전기학회 2011 Journal of Electrical Engineering & Technology Vol.6 No.6

This paper introduces an efficient voltage multiplier circuit for improved voltage gain and power efficiency of radio frequency identification (RFID) tags. The multiplier is fully integratable and takes advantage of both passive and active circuits to reduce the required input power while yielding the desired DC voltage. A six-stage voltage multiplier and an ultralow power voltage regulator are designed in a 0.13 μm complementary metal-oxide semiconductor process for 2.45 GHz RFID applications. The minimum required input power for a 1.2 V supply voltage in the case of a 50 Ω antenna is -20.45 dBm. The efficiency is 15.95% for a 1 MΩ load. The regulator consumes 129 nW DC power and maintains the reference voltage in a 1.1% range with V_dd varying from 0.8 to 2 V. The power supply noise rejection of the regulator is 42 dB near a 2.45 GHz frequency and performs better than -32 dB from 100 Hz to 10 GHz frequencies.

Design of a High Performance Patch Antenna for GPS Communication Systems

Hamedi-Hagh, Sotoudeh,Chung, Joseph,Oh, Soo-Seok,Jo, Ju-Ung,Park, Noh-Joon,Park, Dae-Hee The Korean Institute of Electrical Engineers 2009 Journal of Electrical Engineering & Technology Vol.4 No.2

This paper presents the design of a patch antenna for GPS portable devices. The antenna is designed to operate at Ll band on an FR4 PCB with a thickness of 1.6mm, a dielectric constant of 3.8 and two metallization layers. The antenna has a dimension of 49mm${\times}$36mm and operates at 1.5754GHz with a return loss of -36dB and a measured bandwidth of 250MHz.

Design of UHF CMOS Front-ends for Near-field Communications

Hamedi-Hagh, Sotoudeh,Tabesh, Maryam,Oh, Soo-Seok,Park, Noh-Joon,Park, Dae-Hee The Korean Institute of Electrical Engineers 2011 Journal of Electrical Engineering & Technology Vol.6 No.6

This paper introduces an efficient voltage multiplier circuit for improved voltage gain and power efficiency of radio frequency identification (RFID) tags. The multiplier is fully integratable and takes advantage of both passive and active circuits to reduce the required input power while yielding the desired DC voltage. A six-stage voltage multiplier and an ultralow power voltage regulator are designed in a 0.13 ${\mu}m$ complementary metal-oxide semiconductor process for 2.45 GHz RFID applications. The minimum required input power for a 1.2 V supply voltage in the case of a 50 ${\Omega}$ antenna is -20.45 dBm. The efficiency is 15.95% for a 1 $M{\Omega}$ load. The regulator consumes 129 nW DC power and maintains the reference voltage in a 1.1% range with $V_{dd}$ varying from 0.8 to 2 V. The power supply noise rejection of the regulator is 42 dB near a 2.45 GHz frequency and performs better than -32 dB from 100 Hz to 10 GHz frequencies.

Applications of Nanowire Transistors for Driving Nanowire LEDs

Hamedi-Hagh, Sotoudeh,Park, Dae-Hee The Korean Institute of Electrical and Electronic 2012 Transactions on Electrical and Electronic Material Vol.13 No.2

Operation of liquid crystal displays (LCDs) can be improved by monolithic integration of the pixel transistors with light emitting diodes (LEDs) on a single substrate. Conventional LCDs make use of filters to control the backlighting which reduces the overall efficiency. These LCDs also utilize LEDs in series which impose failure and they require high voltage for operation with a power factor correction. The screen of small hand-held devices can operate from moderate brightness. Therefore, III-V nanowires that are grown along with transistors over Silicon substrates can be utilized. Control of nanowire LEDs with nanowire transistors will significantly lower the cost, increase the efficiency, improve the manufacturing yield and simplify the structure of the small displays that are used in portable devices. The steps to grow nanowires on Silicon substrates are described. The vertical n-type and p-type nanowire transistors with surrounding gate structures are characterized. While biased at 0.5 V, nanowire transistors with minimum radius or channel width have an OFF current which is less than 1pA, an ON current more than 1 ${\mu}A$, a total delay less than 10 ps and a transconductance gain of more than 10 ${\mu}A/V$. The low power and fast switching characteristics of the nanowire transistor make them an ideal choice for the realization of future displays of portable devices with long battery lifetime.

Design of Next Generation Amplifiers Using Nanowire FETs

Hamedi-Hagh, Sotoudeh,Oh, Soo-Seok,Bindal, Ahmet,Park, Dae-Hee The Korean Institute of Electrical Engineers 2008 Journal of Electrical Engineering & Technology Vol.3 No.4

Vertical nanowire SGFETs(Surrounding Gate Field Effect Transistors) provide full gate control over the channel to eliminate short channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10nm channel length and a 2nm channel radius. The amplifier dissipates $5{\mu}W$ power and provides 5THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5V, and a distortion better than 3% from a 1.8V power supply and a 20aF capacitive load. The 2nd and 3rd order harmonic distortions of the amplifier are -40dBm and -52dBm, respectively, and the 3rd order intermodulation is -24dBm for a two-tone input signal with 10mV amplitude and 10GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high speed analog and VLSI technologies.

Preoperative short course radiotherapy with concurrent and consolidation chemotherapies followed by delayed surgery in locally advanced rectal cancer: preliminary results

Aghili, Mahdi,Sotoudeh, Sarvazad,Ghalehtaki, Reza,Babaei, Mohammad,Farazmand, Borna,Fazeli, Mohammad-Sadegh,Keshvari, Amir,Haddad, Peiman,Farhan, Farshid The Korean Society for Radiation Oncology 2018 Radiation Oncology Journal Vol.36 No.1

Purpose: This study aimed to assess complications and outcomes of a new approach, that is, combining short course radiotherapy (SRT), concurrent and consolidative chemotherapies, and delayed surgery. Materials and Methods: In this single arm phase II prospective clinical trial, patients with T3-4 or N+ M0 rectal adenocarcinoma were enrolled. Patients who received induction chemotherapy or previous pelvic radiotherapy were excluded. Study protocol consisted of three-dimensional conformal SRT (25 Gy in 5 fractions in 1 week) with concurrent and consolidation chemotherapies including capecitabine and oxaliplatin. Total mesorectal excision was done at least 8 weeks after the last fraction of radiotherapy. Primary outcome was complete pathologic response and secondary outcomes were treatment related complications. Results: Thirty-three patients completed the planned preoperative chemoradiation and 26 of them underwent surgery (24 low anterior resection and 2 abdominoperineal resection). Acute proctitis grades 2 and 3 were seen in 11 (33.3%) and 7 (21.2%) patients, respectively. There were no grades 3 and 4 subacute hematologic and non-hematologic (genitourinary and peripheral neuropathy) toxicities and perioperative morbidities such as anastomose leakage. Grade 2 or higher late toxicities were observed among 29.6% of the patients. Complete pathologic response was achieved in 8 (30.8%) patients who underwent surgery. The 3-year overall survival and local control rates were 65% and 94%, respectively. Conclusion: This study showed that SRT combined with concurrent and consolidation chemotherapies followed by delayed surgery is not only feasible and tolerable without significant toxicity but also, associated with promising complete pathologic response rates.

Healthy and Unhealthy Dietary Patterns Are Related to Depression: A Case-Control Study

Maryam Khosravi,Gity Sotoudeh,Reza Majdzadeh,Somayeh Nejati,Samaneh Darabi,Firoozeh Raisi,Ahmad Esmaillzadeh,Maryam Sorayani 대한신경정신의학회 2015 PSYCHIATRY INVESTIGATION Vol.12 No.4

ObjectiveaaMajor depressive disorder is the leading cause of disability around the world. The relationship between depression and dietary patterns has been reported in a few studies but with controversial results. This study aimed to investigate this relationship in an Iranian population. MethodsaaIn our study, 330 depressed patients (cases) and healthy people (controls) (1:2) were individually matched according to age, sex and area of residence. New cases of depression were recruited from two psychiatric clinics in Tehran. Interviewers went to each patient’s residential area, and invited qualified individuals to participate in the study as controls. Food intake over the past year was collected using a validated semi quantitative food frequency questionnaire. Dietary patterns were determined by the principal components method. Binary logistic regression was used to test the effect of dietary patterns on depression. ResultsaaWe identified two major dietary patterns by using factor analysis: the healthy and unhealthy dietary patterns. We categorized the scores of these patterns to quartiles. After adjusting for non-depression drug use, job, marital status, children number, and body mass index, the relations of depression and quartiles of two dietary patterns are significant (p=0.04 & p=0.01, respectively). Compared with participants in the lowest quartile, those in the highest quartile had significantly lower odds ratio (OR) for depression in healthy dietary pattern, and higher OR for depression in unhealthy dietary pattern. ConclusionaaThis study indicates that healthy and unhealthy dietary patterns may be associated with the risk of depression. The results can be used for developing interventions that aim to promote healthy eating for the prevention of depression.