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- 저자 : S.Devarajan (검색결과 3 건)
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Chinnaiyah Sripan,Devarajan Alagarasan,S. Varadharajaperumal,R.Ganesan,Ramakanta Naik 한국물리학회 2020 Current Applied Physics Vol.20 No.8
The well-known quaternary Cu2ZnSnS4 (CZTS) chalcogenide thin films are playing an important role in modern technology. The CZTS nanocrystal were successfully prepared by solution method using water, ethylene glycol and ethylenediamine as different solvent. The pure phase material was used for thin film coating by thermal evaporation method. The prepared CZTS thin films were characterized by XRD, Raman spectroscopy, FESEM, XPS and FT-IR spectroscopy. The XRD and Raman spectroscopy analysis revealed the formation of polycrystalline CZTS thin film with tetragonal crystal structure after annealing at 450 °C. The oxidation state of the annealed film was studied by XPS. A direct band gap about 1.36 eV was estimated for the film from FT-IR studies, which is nearly close to the optimum value of band gap energy of CZTS materials for best solar cell efficiency. The CZTS annealed thin films are more suitable for using as a p-type absorber layer in a low-cost solar cell.
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Wafer-Level Three-Dimensional Monolithic Integration for Intelligent Wireless Terminals
Gutmann, R.J.,Zeng, A.Y.,Devarajan, S.,Lu, J.Q.,Rose, K. The Institute of Electronics and Information Engin 2004 Journal of semiconductor technology and science Vol.4 No.3
A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.
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Wafer-Level Three-Dimensional Monolithic Integration for Intelligent Wireless Terminals
R.J.Gutmann,A.Y.Zeng,S.Devarajan,J.-Q.Lu,K.Rose 대한전자공학회 2004 Journal of semiconductor technology and science Vol.4 No.3
A three-dimensional (3D) IC technology platform is presented for high-performance. low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-safer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-nafer via test structure, and compatibility of the proce.. .teps "ith 130 nm CMOS SOl devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wfireless terminalss as vertical integration of processor, large memors, image sensors and RF/microwawe transceiwers can be achieved with silicon-based ICs (Si CMOS and/or SiCe BiCMOS). Two esamples of such capability are<br/> highlighted memory-intenshe Si CCYIOS digital<br/> processors with large L2 caches and SiGe BiCMS pipelined A/D converters. A comparison of wafer-level 3D integration with system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.<br/> Index Terms-3D Integration, wafer bonding, intelligent wireless terminal, memory-intensive digital processors, pipelined A/D converters<br/>
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