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      • KCI등재

        Performance Analysis of a Novel Reduced Switch Cascaded Multilevel Inverter

        R. Nagarajan,M. Saravanan 전력전자학회 2014 JOURNAL OF POWER ELECTRONICS Vol.14 No.1

        Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.

      • SCIESCOPUSKCI등재

        Performance Analysis of a Novel Reduced Switch Cascaded Multilevel Inverter

        Nagarajan, R.,Saravanan, M. The Korean Institute of Power Electronics 2014 JOURNAL OF POWER ELECTRONICS Vol.14 No.1

        Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.

      • KCI등재

        ODD-EVEN GRACEFUL GRAPHS

        R. Sridevi,S. Navaneethakrishnan,A. Nagarajan,K. Nagarajan 한국전산응용수학회 2012 Journal of applied mathematics & informatics Vol.30 No.5

        The Odd-Even graceful labeling of a graph G with q edges means that there is an injection f : V (G) to {1, 3, 5, ... , 2q +1} such that,when each edge uv is assigned the label| f(u) - f(v)|, the resulting edge labels are {2, 4, 6, ..., 2q}. A graph which admits an odd-even graceful labeling is called an odd-even graceful graph. In this paper, we prove that some well known graphs namely Pn, P+n , K1,n, K1,2,n, Km,n, Bm,n are Odd-Even graceful.

      • KCI등재

        ODD-EVEN GRACEFUL GRAPHS

        Sridevi, R.,Navaneethakrishnan, S.,Nagarajan, A.,Nagarajan, K. The Korean Society for Computational and Applied M 2012 Journal of applied mathematics & informatics Vol.30 No.5

        The Odd-Even graceful labeling of a graph G with $q$ edges means that there is an injection $f:V (G)$ to $\{1,3,5,{\cdots},2q+1\}$ such that, when each edge $uv$ is assigned the label ${\mid}f(u)-f(v){\mid}$, the resulting edge labels are $\{2,4,6,{\cdots},2q\}$. A graph which admits an odd-even graceful labeling is called an odd-even graceful graph. In this paper, we prove that some well known graphs namely $P_n$, $P_n^+$, $K_{1,n}$, $K_{1,2,n}$, $K_{m,n}$, $B_{m,n}$ are Odd-Even graceful.

      • KCI등재

        Effect of Geometrical Parameters on Optimal Design of Synchronous Reluctance Motor

        V. S. Nagarajan,V. Kamaraji,M. Balaji,R. Arumugam,N. Ganesh,R. Rahul,M. Lohit 한국자기학회 2016 Journal of Magnetics Vol.21 No.4

        Torque ripple minimization without decrease in average torque is a vital attribute in the design of Synchronous Reluctance (SynRel) motor. As the design of SynRel motor is an arduous task, which encompasses many design variables, this work first analyses the significance of the effect of varying the geometrical parameters on average torque and torque ripple and then proposes an extensive optimization procedure to obtain configurations with improved average torque and minimized torque ripple. A hardware prototype is fabricated and tested. The Finite Element Analysis (FEA) software tool used for validating the test results is MagNet 7.6.0.8. Multi Objective Particle Swarm Optimization (MOPSO) is used to determine the various designs meeting the requirements of reduced torque ripple and improved torque performance. The results indicate the efficacy of the proposed methodology and substantiate the utilization of MOPSO as a significant tool for solving design problems related to SynRel motor.

      • KCI등재

        Surface Passivation Schemes for High-Efficiency c-Si Solar Cells - A Review

        Nagarajan Balaji,이준신,Shahzada Qamar Hussain,박철민,Jayapal Raja,R. Jeyakumar 한국전기전자재료학회 2015 Transactions on Electrical and Electronic Material Vol.16 No.5

        To reduce the cost of solar electricity, the crystalline-silicon (c-Si) photovoltaic industry is moving toward the use of thinner wafers (100 μm to 200 μm) to achieve a high efficiency. In this field, it is imperative to achieve an effective passivation method to reduce the electronic losses at the c-Si interface. In this article, we review the most promising surface passivation schemes that are available for high-efficiency solar cells.

      • KCI등재

        Influence of SF6/N2 Gas Mixture Ratios on the Lightning Streamer Propagation Characteristics of 22 kV MV Circuit Breaker

        R. Gandhi,S. Chandrasekar,C. Nagarajan 대한전기학회 2018 Journal of Electrical Engineering & Technology Vol.13 No.4

        In recent times, gas insulated medium voltage (MV) circuit breakers (CB) form a vital component in power system network, considering its advantages such as reduced size and safety margins. Gas insulation characteristics of circuit breakers are generally measured by lightning impulse (LI) test according to IEC standard 60060-1 as a factory routine test. Considering the environmental issues of SF6 gas, many research works are being carried out towards the mixture of SF6 gases for high voltage insulation applications. However, few reports are only available regarding the LI withstand and streamer propagation characteristics (at both positive and negative polarity of waveform) of SF6/N2 gas mixture insulated medium voltage circuit breakers. In this paper, positive and negative polarity LI tests are carried out on 22 kV medium voltage circuit breaker filled with SF6/N2 gas mixture at different gas pressures (1-5 bar) and at different gas mixture ratios. Important LI parameters such as breakdown voltage, streamer velocity, time to breakdown and acceleration voltage are evaluated with IEC standard LI (1.2/50 µs) waveform. Weibull distribution analysis of LI breakdown voltage data is carried out and 50% probability breakdown voltage, scale parameter and shape parameter are evaluated. Results illustrate that the 25% SF6+75%N2 gas filled insulation considerably enhances the LI withstand and breakdown strength of MV circuit breakers. LI breakdown voltage of circuit breaker under negative polarity shows higher value when compared with positive polarity. Results show that maintaining the gas pressure at 0.3 MPa (3 bar) with 10% SF6 gas mixed with 90% N2 will give optimum lighting impulse withstand performance of 22 kV MV circuit breaker.

      • KCI등재

        Electrical and optical characterization of SiOxNy and SiO2 dielectric layers and rear surface passivation by using SiO2/SiOxNy stack layers with screen printed local Al-BSF for c-Si solar cells

        Nagarajan Balaji,Huong Thi Thanh Nguyen,박철민,주민규,Jayapal Raja,Somenath Chatterjee,R. Jeyakumar,이준신 한국물리학회 2018 Current Applied Physics Vol.18 No.1

        In c-Si solar cells, surface recombination velocity increases as the wafer thickness decreases due to an increase in surface to volume ratio. For high efficiency, in addition to low surface recombination velocity at the rear side, a high internal reflection from the rear surface is also required. The SiOxNy film with low absorbance can act as rear surface reflector. In this study, industrially feasible SiO2/SiOxNy stack for rear surface passivation and screen printed local aluminium back surface field were used in the cell structure. A 3 nm thick oxide layer has resulted in low fixed oxide charge density of 1.58 1011 cm2 without parasitic shunting. The oxide layer capped with SiOxNy layer led to surface recombination velocity of 155 cm/s after firing. Using single layer (SiO2) rear passivation, an efficiency of 18.13% has been obtained with Voc of 625 mV, Jsc of 36.4 mA/cm2 and fill factor of 78.7%. By using double layer (SiO2/SiOxNy stack) passivation at the rear side, an efficiency of 18.59% has been achieved with Voc of 632 mV, Jsc of 37.6 mA/ cm2, and fill factor of 78.3%. An improved cell performance was obtained with SiO2/SiOxNy rear stack passivation and local BSF.

      • Secure Data Transmission using Content Fingerprinting Digital Watermarking Techniques

        R.Gayathri,V.Nagarajan 대한전자공학회 2015 ITC-CSCC :International Technical Conference on Ci Vol.2015 No.6

        In order to hinder the unauthorized redistribution of digital data, digital watermarking has increasingly applied to conceal information in digital multimedia data, thus enlisting the watermarking technology in the difficult fight against intellectual property rights infringement. Brought up by the crucial issue of copyright, digital watermarking plays a key role in protecting integrity and providing authorization for multimedia. Fingerprinting is a means to trace the illegally redistributed intellectual property (IP) by creating a unique IP instance with a different signature for each user. Existing fingerprinting techniques focus on lowering the design effort to create a large number of different IP instances without paying much attention on the ease of fingerprint detection upon IP integration. A new framework that enhances the Mobile commerce by the use of content fingerprinting and digital watermarking techniques provides security and privacy to the content owner. The content fingerprinting technique is based on active content fingerprinting in which fingerprint can be hided into image using reversible watermarking of haar transform for secure transmission. The performance of this system can be examined based on peak signal to noise ratio and mean square error and it can be compared with existing methods. Thus digital watermarking technology can be introduced into the field of mobile commerce to provide high level of security for online transactions.

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