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Analysis of Trapped Charges in Dopant-Segregated Schottky Barrier-Embedded FinFET SONOS Devices
Sung-Jin Choi,Jin-Woo Han,Moongyu Jang,Yang-Kyu Choi IEEE 2009 IEEE electron device letters Vol.30 No.10
<P>The aim of this letter is to analyze the spatial distribution of trapped charges in the type of dopant-segregated Schottky barrier (DSSB)-embedded FinFET SONOS devices used in NAND-type flash memory. Due to localized programming by carrier injection with extra kinetic energy, the spatial distribution of electrons trapped in an O/N/O layer of a DSSB SONOS device after a short time of programming differs from that in an O/N/O layer of a conventional SONOS device, which results in the degradation of subthreshold slope (SS). Note that the degraded SS recovers as the program time increases. The measured and simulated data confirm that the high speed of the programming is due largely to the localized trapped charges injected from DSSB source/drain junctions.</P>
Dopant-Segregated Schottky Source/Drain FinFET With a NiSi FUSI Gate and Reduced Leakage Current
Sung-Jin Choi,Jin-Woo Han,Sungho Kim,Dong-Il Moon,Moongyu Jang,Yang-Kyu Choi IEEE 2010 IEEE transactions on electron devices Vol.57 No.11
<P>Enhanced Dopant-segregated Schottky-barrier (DSSB) FinFETs combined with a fully silicided (FUSI) gate were fabricated via single-step Ni-silicidation. Both workfunction control of the gate and a lowered effective SB-height in the source/drain junctions are simultaneously achieved by the dopant-segregated silicidation process. Moreover, the leakage current was significantly reduced with the aid of deep source/drain implantation. Therefore, it can be expected that a DSSB device with a FUSI gate have several advantages as both a logic and nonvolatile memory device. First, for a logic device, it can provide low parasitic resistance and a tunable threshold voltage. Second, for a nonvolatile memory device, the increased workfunction due to the FUSI gate can enhance the erasing characteristics by suppressing the back tunneling of electrons from the gate side as well as the programming characteristics.</P>
P-Channel Nonvolatile Flash Memory With a Dopant-Segregated Schottky-Barrier Source/Drain
Sung-Jin Choi,Jin-Woo Han,Dong-Il Moon,Sungho Kim,Moongyu Jang,Yang-Kyu Choi IEEE 2010 IEEE transactions on electron devices Vol.57 No.8
<P>A p-channel dopant-segregated-Schottky-barrier (DSSB) device based on a SOI FinFET structure is proposed for silicon-oxide-nitride-oxide-silicon type Flash memory, providing the feasibility of bit-by-bit operation through the aid of a symmetric program/erase operation. This concept is based on utilizing injected holes due to enhanced Fowler-Nordheim tunneling probability triggered by the sharpened energy band bending at the DSSB source/drain junctions as a programming method and the tunneled electrons from a silicon channel as an erasing method. As a result, a threshold voltage window of nearly 4 V and good data retention are achieved within a P/E time of 3.2 μs.</P>
Sung-Jin Choi,Jin-Woo Han,Sungho Kim,Dong-Il Moon,Moongyu Jang,Yang-Kyu Choi IEEE 2010 IEEE electron device letters Vol.31 No.3
<P>A high-performance polycrystalline silicon (poly-Si) thin-film transistor (TFT) with Schottky-barrier (SB) source/drain (S/D) junctions is proposed. A p-channel operation on the intrinsic nickel (Ni) silicided S/D was successfully realized with the aid of a thin active layer, despite the fact that the Ni silicided material shows a high SB height (SBH) for holes. Furthermore, for n-channel operation, the dopant-segregation technique implemented on the intrinsic Ni silicide was utilized to reduce the effective SBH for electrons. The results show a higher on-current due to the lower parasitic resistance as well as superior immunity against short-channel effects, compared to the conventional poly-Si TFT composed of p-n S/D junctions.</P>
Sung-Jin Choi,Jin-Woo Han,Dong-Il Moon,Moongyu Jang,Yang-Kyu Choi IEEE 2010 IEEE electron device letters Vol.31 No.1
<P>This letter is aimed at experimentally investigating the fin width (W<SUB>fin</SUB>) dependence of both a dopant-segregated Schottky-barrier (DSSB) and a conventional FinFET SONOS device with diffused p-n junctions for application of a NOR-type flash memory device. High parasitic resistance (R<SUB>para</SUB>) at the source/drain by a narrowed W<SUB>fin</SUB> results in degradation of memory performance for the conventional FinFET SONOS device. In contrast, it is shown that a narrow W<SUB>fin</SUB> significantly improves the memory performance for the DSSB FinFET SONOS device, resulting from an improved lateral electric field without a significant change of the R<SUB>para</SUB> value.</P>
Analysis of Transconductance <tex> $(g_{m})$</tex> in Schottky-Barrier MOSFETs
Sung-Jin Choi,Chel-Jong Choi,Jee-Yeon Kim,Moongyu Jang,Yang-Kyu Choi IEEE 2011 IEEE transactions on electron devices Vol.58 No.2
<P>This paper experimentally investigates the unique behavior of transconductance (<I>gm</I>) in the Schottky-barrier metal-oxide-semiconductor field-effect transistors (SB-MOSFETs) with various silicide materials. When the Schottky-barrier height (SBH) or a scaling parameter is not properly optimized, a peculiar shape of <I>gm</I> is observed. Thus, <I>gm</I> can be used as a novel metric that exhibits the transition of the carrier injection mechanisms from a thermionic emission (TE) to thermally assisted tunneling (TU) in the SB-MOSFETs. When the local maximum point of <I>gm</I> is observed, it can be expected that an incomplete transition occurs between TE and TU in SB-MOSFETs. When a dopant-segregation (DS) technique is implemented in the SB-MOSFETs, however, the carrier injection efficiency from the source to the channel is significantly improved, although the SBH is not minimized. As a consequence, the peculiar shape of the <I>gm</I> disappears, i.e., a complete transition from TE to TU can be enabled by the DS technique.</P>
Schottky Barrier MOSFETs with High Current Drivability for Nano-regime Applications
Moongyu Jang,Yarkyeon Kim,Myungsim Jun,Cheljong Choi,Taeyoub Kim,Byoungchul Park,Seongjae Lee 대한전자공학회 2006 Journal of semiconductor technology and science Vol.6 No.1
Various sizes of erbium/platinum silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from 20μm to 10nm. The manufactured SB-MOSFETs show excellent DIBL and subthreshold swing characteristics due to the existence of Schottky barrier between source and channel. It is found that the minimization of trap density between silicide and silicon interface and the reduction of the underlap resistance are the key factors for the improvement of short channel characteristics. The manufactured 10 nm n-type SBMOSFET showed 550μA/um saturation current at VGS-VT = VDS = 2V condition (Tox = 5nm) with excellent short channel characteristics, which is the highest current level compared with reported data.
Choi, Eunyoung,Park, Sungmin,Ahn, Hyungju,Lee, Moongyu,Bang, Joona,Lee, Byeongdu,Ryu, Du Yeol American Chemical Society 2014 Macromolecules Vol.47 No.12
<P>Lamellar microdomain orientation in polystyrene-<I>b</I>-poly(methyl methacrylate) (PS-<I>b</I>-PMMA) films was controlled by a solvent vapor annealing process, where the high-molecular-weight block copolymer (BCP) was used to self-assemble in a large period of 105 nm. A neutral solvent annealing with tetrahydrofuran vapor screened the difference in the surface energy between the two blocks and the interfacial interactions of the substrate with each block, leading to the substrate-independent perpendicular orientation of lamellar microdomains. Together with thermal annealing of the solvent-annealed BCP film, we demonstrate that highly ordered line arrays of perpendicularly oriented lamellae were well guided in topographic line and disk photoresist patterns composed of the PS-attractive cross-linked copolymer, where the interlamellar <I>d</I>-spacing compliant to the patterns was dependent on the confinement types.</P><P><B>Graphic Abstract</B> <IMG SRC='http://pubs.acs.org/appl/literatum/publisher/achs/journals/content/mamobx/2014/mamobx.2014.47.issue-12/ma500716f/production/images/medium/ma-2014-00716f_0009.gif'></P><P><A href='http://pubs.acs.org/doi/suppl/10.1021/ma500716f'>ACS Electronic Supporting Info</A></P>
Jang, Moongyu,Park, Youngsam,Jun, Myungsim,Hyun, Younghoon,Choi, Sung-Jin,Zyung, Taehyoung Springer 2010 NANOSCALE RESEARCH LETTERS Vol.5 No.10
<P>Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 μV/K for p-leg and −94 μV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K<SUP>2</SUP> at room temperature.</P>