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Digital Audio Effect System-on-a-Chip Based on Embedded DSP Core
Kyungjin Byun,Young-Su Kwon,Seongmo Park,엄낙웅 한국전자통신연구원 2009 ETRI Journal Vol.31 No.6
This paper describes the implementation of a digital audio effect system-on-a-chip (SoC), which integrates an embedded digital signal processor (DSP) core, audio codec intellectual property, a number of peripheral blocks, and various audio effect algorithms. The audio effect SoC is developed using a software and hardware co-design method. In the design of the SoC, the embedded DSP and some dedicated hardware blocks are developed as a hardware design, while the audio effect algorithms are realized using a software centric method. Most of the audio effect algorithms are implemented using a C code with primitive functions that run on the embedded DSP, while the equalization effect, which requires a large amount of computation, is implemented using a dedicated hardware block with high flexibility. For the optimized implementation of audio effects, we exploit the primitive functions of the embedded DSP compiler, which is a very efficient way to reduce the code size and computation. The audio effect SoC was fabricated using a 0.18 µm CMOS process and evaluated successfully on a real-time test board.
Byun, Yong-Soo,Rho, Chang Rae,Cho, Kyungjin,Choi, Jin A,Na, Kyung Sun,Joo, Choun-Ki The Korean Ophthalmological Society 2011 Korean Journal of Ophthalmology Vol.25 No.6
<P><B>Purpose</B></P><P>To assess the effectiveness and tolerability of cyclosporine ophthalmic emulsion (CsA) 0.05% in patients with moderate to severe dry eye disease in Korea.</P><P><B>Methods</B></P><P>This was a prospective, multicenter, open-label, surveillance study of 392 Korean patients with moderate to severe dry eye disease who were treated with CsA 0.05% for three months. An assessment of effectiveness was performed at baseline, and after 1, 2, and 3 months. The primary effectiveness outcomes were changes in ocular symptoms and Schirmer score. The secondary effectiveness outcomes were a change in conjunctival staining, use of artificial tears, global evaluation of treatment, and patient satisfaction. The primary safety outcome was the incidence and nature of adverse events.</P><P><B>Results</B></P><P>A total of 362 patients completed the study. After three months, all ocular symptom scores were significantly reduced compared to the baseline values, while the Schirmer scores were significantly increased relative to baseline (<I>p</I> < 0.0001). After three months, there were significant reductions from baseline in conjunctival staining (<I>p</I> < 0.01) and use of artificial tears (<I>p</I> < 0.0001). According to clinicians' global evaluations, most patients (>50%) experienced at least a 25% to 50% improvement in symptoms from baseline at each follow-up visit. The majority of patients (72.0%) were satisfied with the treatment results, and 57.2% reported having no or mild symptoms after treatment. The most common adverse events were ocular pain (11.0%).</P><P><B>Conclusions</B></P><P>Our findings indicate that CsA 0.05% is an effective and tolerable treatment for dry eye disease in Korean clinical practice.</P>
Energy-efficient static sparse-tree adder based on MUX-less bypassing architecture
Seongrim Choi,Jonghun Ahn,Kyungjin Byun,Byeong-Gyu Nam IET 2014 Electronics letters Vol.50 No.25
<P>An energy-efficient 64 bit static sparse-tree adder using a multiplexer (MUX)-less bypassing scheme is proposed for mobile central processing units. Conventionally, bypassing schemes have been used to eliminate unnecessary switching of circuits but have incorporated a large delay overhead due to their output MUX, which reduces the energy efficiency of circuits in terms of power-delay product (PDP). A novel static sparse-tree adder is presented based on a proposed MUX-less bypassing scheme to reduce the delay associated with the conventional bypassing scheme, thereby improving the energy efficiency, i.e. the PDP. Simulation results show a 30% reduction in PDP compared to the conventional bypassing adder and a 13% reduction from the state-of-the-art technique.</P>
High Performance and FPGA Implementation of Scalable Video Encoder
Park, Seongmo,Kim, Hyunmi,Byun, Kyungjin The Institute of Electronics and Information Engin 2014 IEIE Transactions on Smart Processing & Computing Vol.3 No.6
This paper, presents an efficient hardware architecture of high performance SVC(Scalable Video Coding). This platform uses dedicated hardware architecture to improve its performance. The architecture was prototyped in Verilog HDL and synthesized using the Synopsys Design Compiler with a 65nm standard cell library. At a clock frequency of 266MHz, This platform contains 2,500,000 logic gates and 750,000 memory gates. The performance of the platform is indicated by 30 frames/s of the SVC encoder Full HD($1920{\times}1080$), HD($1280{\times}720$), and D1($720{\times}480$) at 266MHz.
Enhancing Tumor Perfusion Using Orally Active Heparin to Improve the Efficacy of Immunotherapy
Jeong Uk CHOI,Na Kyeong LEE,Hyungseok SEO,Seung Woo CHUNG,Taslim A. AL-HILAL,Seho KWEON,Sang Kyoon KIM,Seohyun AHN,Uk-Il KIM,Jin Woo PARK,Chang-Yuil KANG,In-San KIM,Kyungjin KIM,Youngro BYUN 한국생물공학회 2022 한국생물공학회 학술대회 Vol.2022 No.4