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Lee, June-Kyoo,Park, Kyung-Woo,Kim, Hak-Rin,Kong, Seong-Ho The Korean Infomation Display Society 2010 Journal of information display Vol.11 No.2
This paper presents the effects of a dielectric layer and an electrolyte on the driving performance of an electrowetting on dielectric (EWOD)-based liquid lens. The range of tunable focal length of the EWOD-based liquid lens was highly dependent on the conditions of the dielectric layer, which included an inorganic oxide layer and an organic hydrophobic layer. Moreover, experiments on the physical and optical durability of electrolyte by varying temperature conditions, were conducted and their results were discussed. Finally, the lens with a truncated-pyramid silicon cavity having a sidewall dielectrics and electrode was fabricated by anisotropic etching and other micro-electromechanical systems (MEMS) technologies in order to demonstrate its performance. The lens with $0.6-{\mu}m$-thick $SiO_2$ layer and 10 wt% LiCl-electrolyte exhibited brilliant focal-length tunability from infinity to 3.19 mm.
이준규(June Kyoo Lee),박경우(Kyung-Woo Park),강현오(Hyun Oh Kang),김재건(Jae Kun Kim),김학린(Hak-Rin Kim),공성호(Seong Ho Kong) 대한전기학회 2009 대한전기학회 학술대회 논문집 Vol.2009 No.7
기존의 초소형 렌즈모듈들은 초점 거리 가변을 위한 구동 장치가 필요하여 소형화 한계, 큰 전력소모, 부품의 기계적 결함 등 해결해야 할 부가적인 문제점들이 존재하였다. 액체렌즈는 이러한 문제를 해결할 수 있는 유력한 기술로 주목받고 있으며, 특히 부가적인 구동 장치가 필요없고 비교적 간단한 원리로 렌즈 곡률을 조절할 수 있는 일렉트로웨팅 기반의 액체렌즈는 초점 거리 조절 및 줌 조절이 필요한 휴대폰, 캡슐 내시경 등에 적용이 가능하다. 그러나 기존의 일렉트로웨팅 기반의 액체렌즈는 렌즈 캐비티의 크기에서 큰 단점이 있으며, 렌즈모듈구성 시에도 소형화하는데 한계가 존재하였다. 본 연구에서는 렌즈 캐비티를 MEMS 기술을 이용하여 실리콘 기판 상에 제작함으로써 구동회로의 집적이 가능한 액체렌즈를 제작하였다.
A SSN-Reduced 5Gb/s Parallel Transmitter
Seon-Kyoo Lee,Young-Sang Kim,Hong-June Park,Jae-Yoon Sim 대한전자공학회 2007 Journal of semiconductor technology and science Vol.7 No.4
A current-balancing segmented groupinverting transmitter is presented for multi-Gb/s single-ended parallel links. With an additional increase of 4 pins, 16-bit data is efficiently encoded to 20 pins to achieve the current balancing and eliminate the simultaneous switching noise. Since the proposed coding is a simple inversion-or-not transformation of pre-defined groups of binary data, it can be implemented with simplified logic circuits. The transmitter is designed with a 0.18μm CMOS technology, and simulated eye diagrams at 5Gb/s show dramatic improvements in signal integrity.
A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation
Seon-Kyoo Lee,Byungsub Kim,Hong-June Park,Jae-Yoon Sim IEEE 2013 IEEE journal of solid-state circuits Vol.48 No.9
<P>This paper presents an adaptive far-end crosstalk cancellation scheme for a single-ended parallel receiver. The adaptation engine is embedded in a single representative channel CDR, and the receiver efficiently reduces the crosstalk noise with a minimal cost in hardware and power consumption. In addition, the proposed scheme can be applied to any given CDR and equalizing circuits. The receiver is fabricated in 0.13 μm CMOS technology and achieves a reduction of FEXT-induced jitter up to 75%. The receiver consumes 65 mW at 5 Gb/s (4.3 mW/Gb/s/pin) including a PLL for global clock distribution.</P>
A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 <tex> $\mu$</tex> m CMOS
Seon-Kyoo Lee,Young-Hun Seo,Hong-June Park,Jae-Yoon Sim IEEE 2010 IEEE journal of solid-state circuits Vol.45 No.12
<P>An all-digital PLL for wireline applications is designed with a sub-exponent TDC which adaptively scales its resolution according to input time difference. By cascading 2× time amplifiers, the TDC efficiently generates the exponent-only information for fractional time difference. To improve linearity in a wide input range, a replica-based self-calibration scheme is applied to the time amplifier. The TDC, implemented in a 0.18 μm CMOS, shows the minimum resolution of 1.25 ps with a total conversion range of 2.5 ns, the maximum operating frequency of 250 MHz, and power consumption of 1.8 mW at 60 MHz. The measured rms jitter of PLL was 5.03 ps at 960 MHz.</P>
Seon-Kyoo Lee,Byungsub Kim,Hong-June Park,Jae-Yoon Sim IEEE 2013 IEEE transactions on circuits and systems. a publi Vol.60 No.2
<P>This brief presents an 8-bit parallel transceiver for low-power memory interface with a current-regulated voltage-mode driver and a clock and data recovery performing both bit recovery and byte alignment. Sharing a current source by output drivers enables voltage swing control without any regulator circuit while holding the benefits of low-power voltage-mode driving. In the receiver, with only one phase rotator in a globally shared phase-locked loop, a narrow-range delay line in each deskewing phase recovery loop effectively performs seamless phase adjustment. The transceiver, implemented in a 90-nm CMOS, shows a data rate of 6 Gbit/s/ch with a bit error rate of 10<SUP>-12</SUP> and a power consumption of 2.8 mW/Gbit/s.</P>