Modeling and Measurement of Radiated Field Emission From a Power/Ground Plane Cavity Edge Excited by a Through-Hole Signal Via Based on a Balanced TLM and Via Coupling Model

Pak, Jun So,Kim, Hyungsoo,Lee, Junwoo,Kim, Joungho Institute of Electrical and Electronics Engineers 2007 IEEE transactions on advanced packaging Vol.30 No.1

<P>A balanced transmission line model (TLM) and via coupling model is proposed for efficient simulation of radiated field emission from a power/ground plane cavity edge, where the radiated field emission is excited by a through-hole signal via in a multilayer package and printed circuit board (PCB). The radiated field emission is simulated and measured with a series of test boards. The simulation agrees fairly well with the measurement confirming the preciseness and usefulness of the proposed model. It is shown that the through-hole signal via is a considerable source of the radiated field emission as well as the signal loss. When the signal trace is switching vertically stacked reference planes, the signal return current path is disconnected at the via and the impedance becomes extremely high. A significant amount of insertion loss and radiated field emission is generated at resonance frequencies of the plane cavity. The effect of a decoupling capacitor fence (De-Cap Fence) at the edge of the board to mitigate the radiated field emission is examined. The proposed model confirms that the De-Cap Fence changes the resonance mode and frequency of the plane cavity, and reduces the radiated field emission</P>

Imaging Findings of Peripheral Arterial Disease on Lower-Extremity CT Angiography Using a Virtual Monoenergetic Imaging Algorithm

Jun Seong Kim,So Hyun Park,Suyoung Park,Jung Han Hwang,Jeong Ho Kim,Seong Yong Pak,Kihyun Lee,Bernhard Schmidt 대한영상의학회 2022 대한영상의학회지 Vol.83 No.5

Peripheral arterial disease (PAD) is common in elderly patients. Lower-extremity CT angiography (LE-CTA) can be useful for detecting PAD and planning its treatment. PAD can also be accurately evaluated on reconstructed monoenergetic images (MEIs) from low kiloelectron volt (keV) to high keV images using dualenergy CT. Low keV images generally provide higher contrast than high keV images but also feature more severe image noise. The noise-reduced virtual MEI reconstruction algorithm, called the Mono+ technique, was recently introduced to overcome such image noise. Therefore, this pictorial review aimed to present the imaging findings of PAD on LE-CTA and compare low and high keV images with those subjected to the Mono+ technique. We found that, in many cases, the overall and segmental image qualities were better and metal artifacts and venous contamination were decreased in the high keV images.

High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)

Joohee Kim,Jun So Pak,Jonghyun Cho,Eakhwan Song,Jeonghyeon Cho,Heegon Kim,Taigon Song,Junho Lee,Hyungdong Lee,Kunwoo Park,Seungtaek Yang,Min-Suk Suh,Kwang-Yoo Byun,Joungho Kim IEEE 2011 IEEE transactions on components, packaging, and ma Vol.1 No.2

<P>We propose a high-frequency scalable electrical model of a through silicon via (TSV). The proposed model includes not only the TSV, but also the bump and the redistribution layer (RDL), which are additional components when using TSVs for 3-D integrated circuit (IC) design. The proposed model is developed with analytic <I>RLGC</I> equations derived from the physical configuration. Each analytic equation is proposed as a function of design parameters of the TSV, bump, and RDL, and is therefore, scalable. The scalability of the proposed model is verified by simulation from the 3-D field solver with parameter variations, such as TSV diameter, pitch between TSVs, and TSV height. The proposed model is experimentally validated through measurements up to 20 GHz with fabricated test vehicles of a TSV channel, which includes TSVs, bumps, and RDLs. Based on the proposed scalable model, we analyze the electrical behaviors of a TSV channel with design parameter variations in the frequency domain. According to the frequency-domain analysis, the capacitive effect of a TSV is dominant under 2 GHz. On the other hand, as frequency increases over 2 GHz, the inductive effect from the RDLs becomes significant. The frequency dependent loss of a TSV channel, which is capacitive and resistive, is also analyzed in the time domain by eye-diagram measurements. Due to the frequency dependent loss, the voltage and timing margins decrease as the data rate increases.</P>

Through-Silicon-Via-Based Decoupling Capacitor Stacked Chip in 3-D-ICs

Eunseok Song,Kyoungchoul Koo,Jun So Pak,Joungho Kim IEEE 2013 IEEE transactions on components, packaging, and ma Vol.3 No.9

<P>In this paper, a new decoupling capacitor stacked chip (DCSC) based on extra decoupling capacitors and through-silicon-vias (TSVs) is proposed to overcome the narrow-bandwidth limitation of the conventional decoupling capacitor solutions in three-dimensional-integrated circuits (3-D-ICs), as exhibited by expensive on-chip metal-oxide-semiconductor (MOS) decoupling capacitors and inductive off-chip discrete decoupling capacitors. In particular, in comparison to the on-chip decoupling solutions, such as MOS, metal-insulator-metal and deep trench capacitors, the proposed TSV-based DCSC represents several advantages, such as small leakage currents, large capacitances ranging from tens of nF to a few μF, low equivalent series inductance (ESL) with tens of pH, and high flexibility in TSV arrangements. The proposed TSV-based DCSC can be applied by mounting decoupling capacitors, such as Si-based MOS capacitors and discrete capacitors, on the backside of a chip and connecting the capacitors to the on-chip power delivery network (PDN) through TSVs. To demonstrate the performance of the proposed DCSC structure, a segmentation method was applied to compare the PDN impedance (Z11) of the TSV-based DCSC with those of the well-known conventional decoupling capacitor methods. The TSV-based DCSC was found to exhibit the advantages of both low on-chip level ESL (under several tens of pH) and high off-chip level capacitance (up to several μF). Additionally, the PDN impedance properties of the TSV-based DCSC were analyzed with respect to the variations in the number of power/ground TSV pairs, on-chip PDN size, and capacitance values of the stacked off-chip discrete decoupling capacitors using the segmentation method.</P>

Modeling of an On-Chip Power/Ground Meshed Plane Using Frequency Dependent Parameters

Chulsoon Hwang,Kiyeong Kim,Jun So Pak,Joungho Kim 한국전자파학회JEES 2011 Journal of Electromagnetic Engineering and Science Vol.11 No.3

This paper proposes a new modeling method for estimating the impedance of an on-chip power/ground meshed plane. Frequency dependent R, L, and C parameters are extracted based on the proposed method so that the model can be applied from DC to high frequencies. The meshed plane model is composed of two parts: coplanar multi strip (CMS) and conductor-backed CMS. The conformal mapping technique and the scaled conductivity concept are used for accurate modeling of the CMS. The developed microstrip approach is applied to model the conductor-backed CMS. The proposed modeling method has been successfully verified by comparing the impedance of RLC circuit based on extracted parameters and the simulated impedance using a 3D-field solver.

Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring

Jonghyun Cho,Eakhwan Song,Kihyun Yoon,Jun So Pak,Joohee Kim,Woojin Lee,Taigon Song,Kiyeong Kim,Junho Lee,Hyungdong Lee,Kunwoo Park,Seungtaek Yang,Minsuk Suh,Kwangyoo Byun,Joungho Kim IEEE 2011 IEEE transactions on components, packaging, and ma Vol.1 No.2

<P>In three-dimensional integrated circuit (3D-IC) systems that use through-silicon via (TSV) technology, a significant design consideration is the coupling noise to or from a TSV. It is important to estimate the TSV noise transfer function and manage the noise-tolerance budget in the design of a reliable 3D-IC system. In this paper, a TSV noise coupling model is proposed based on a three-dimensional transmission line matrix method (3D-TLM). Using the proposed TSV noise coupling model, the noise transfer functions from TSV to TSV and TSV to the active circuit can be precisely estimated in complicated 3D structures, including TSVs, active circuits, and shielding structures such as guard rings. To validate the proposed model, a test vehicle was fabricated using the Hynix via-last TSV process. The proposed model was successfully verified by frequency- and time-domain measurements. Additionally, a noise isolation technique in 3D-IC using a guard ring structure is proposed. The proposed noise isolation technique was also experimentally demonstrated; it provided -17 dB and -10dB of noise isolation between the TSV and an active circuit at 100 MHz and 1 GHz, respectively.</P>

Modeling and Analysis of Power Supply Noise Imbalance on Ultra High Frequency Differential Low Noise Amplifiers in a System-in-Package

Kyoungchoul Koo,Yujeong Shim,Changwook Yoon,Jaemin Kim,Jeongsik Yoo,Jun So Pak,Joungho Kim IEEE 2010 IEEE TRANSACTIONS ON ADVANCED PACKAGING Vol.33 No.3

<P>In this paper, we analyze the power supply noise imbalance and its effects on simultaneous switching noise coupling to an ultra high frequency differential low noise amplifier (LNA) in a system-in-package (SiP) through an off-chip power distribution network (PDN). On and off-chip sources of power supply noise imbalance in a LNA in a SiP were analyzed. A simultaneous switching noise coupling coefficient for the differential LNA output caused by power supply noise imbalance was simulated through co-modeling a hierarchical on and off-chip PDN. The simulation results were validated by measuring the simultaneous switching noise coupling voltage at the differential LNA output. Further validation of four types of a LNA with different PDN designs demonstrates that simultaneous switching noise coupling to the differential LNA output caused by power supply noise imbalance highly depends on the design of the PDN of the SiP.</P>

Effect of the Shield Layer on Signal Interference for 3-D Integration

Doo-Yun Chung,Chun-Bae Park,이종호,Joungho Kim,Jun-So Pak 한국물리학회 2004 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.44 No.1

In this research, we analyzed signal interference by using a test sample for 3-dimensional integration. N+ poly-Si was used as a shield layer between the top and the bottom electrodes. Samples were fabricated and measured to check the interference and to characterize the role of the polysilicon shield layer. As an example, the S-parameters were measured at the wafer level by using a network analyzer. The interference was characterized in terms of the oxide thickness between the electrodes, the doping concentration and the thickness of the poly-Si shield layer, and the overlap area between the electrodes and the shield layer. In this research, we analyzed signal interference by using a test sample for 3-dimensional integra- tion. N + poly-Si was used as a shield layer between the top and the bottom electrodes. Samples were fabricated and measured to check the interference and to characterize the role of the polysil- icon shield layer. As an example, the S-parameters were measured at the wafer level by using a network analyzer. The interference was characterized in terms of the oxide thickness between the electrodes, the doping concentration and the thickness of the poly-Si shield layer, and the overlap area between the electrodes and the shield layer.

High-Frequency Scalable Modeling and Analysis of a Differential Signal Through-Silicon Via

Joohee Kim,Jonghyun Cho,Joungho Kim,Jong-Min Yook,Jun Chul Kim,Junho Lee,Kunwoo Park,Jun So Pak IEEE 2014 IEEE transactions on components, packaging, and ma Vol.4 No.4

<P>An analytic scalable model of a differential signal through-silicon via (TSV) is proposed. This TSV is a ground-signal-signal-ground (GSSG)-type differential signal TSV. Each proposed analytical equation in the model is a function of the structural and material design parameters of the TSV and the bump, which is scalable. The proposed model is successfully validated with measurements up to 20 GHz for the fabricated test vehicles. Additionally, the scalability of the proposed model is verified with simulations by using Ansoft HFSS to vary the design parameters, such as the TSV diameter, pitch between TSVs, and TSV oxide thickness. On the basis of the proposed scalable model, the electrical behaviors of the GSSG-type differential signal TSV are analyzed with respect to the design variations in the frequency domain. Additionally, the electrical performances of a GSSG-type differential signal TSV are evaluated and compared to that of a ground-signal-ground-type single-ended signal TSV, such as insertion loss, characteristic impedance, voltage/timing margin, and noise immunity.</P>

An On-Chip Electromagnetic Bandgap Structure using an On-Chip Inductor and a MOS Capacitor

Chulsoon Hwang,Yujeong Shim,Kyoungchoul Koo,Myunghoi Kim,Jun So Pak,Joungho Kim IEEE 2011 IEEE microwave and wireless components letters Vol.21 No.8

<P>An on-chip electromagnetic bandgap (EBG) structure using a CMOS process is proposed. The proposed structure is the first EBG structure devised to suppress simultaneous switching noise coupling in an on-chip power distribution network (PDN). The on-chip EBG structure utilizes an on-chip inductor and a MOS capacitor to generate a stopband with a range of several GHz in an extremely small size; thus, the EBG structure can be embedded in on-chip PDNs. The proposed on-chip EBG structure was fabricated using a MagnaChip 0.18 μm CMOS process, and we successfully verified a 9.24 GHz stopband, from 1.26 to 10.5 GHz, with an isolation level of 50 dB.</P>