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RISS 인기검색어
- 검색키워드
- 저자 : Ipsita Singh (검색결과 3 건)
- 무료
- 기관 내 무료
- 유료
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A Hardware-in–the-Loop Simulation Approach for Analysis of Permanent Magnet Synchronous Motor Drive
Ipsita Mishra,Ravi Nath Tripathi,Vijay Kumar Singh,Tsuyoshi Hanamoto 전력전자학회 2019 ICPE(ISPE)논문집 Vol.2019 No.5
A hardware-in-the-loop (HIL) simulation approach providing a platform to develop a controller prototype as well as emulators for motor system and power electronic converters that allows rapid testing and proactive system evaluation with an advantage of low cost, safety, and flexibility to operate in extreme boundary conditions. However, the variety of HIL combinations can be adopted to realize a system model that is neither too simple nor to be highly complex to match the realistic behavior considering transient condition and steady state condition. In this paper, a discrete time simulation model of the permanent magnet synchronous motor (PMSM) drive system is presented for FPGA HIL simulation. Moreover, different combination of HIL approach is adopted for detailed performance analysis considering transient behavior of the system. The entire system is implemented using the MATLAB/Simulink and system generator platform provided by Xilinx for HIL simulation using FPGA.
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Network Security in Embedded System Using TLS
Vivek Negi,Himanshu Verma,Ipsita Singh,Aditya Vikram,Kanika Malik,Archana Singh,Gaurav Verma 보안공학연구지원센터 2016 International Journal of Security and Its Applicat Vol.10 No.2
Security in terms of Networks have turn out to be more significant to Organizations, Military and personal computer user’s. Since various kinds of threats are for data from sending it from sender side over internet till it reaches to receiver. Here we will focus on SSL it is a technique used to give client and server authentication, data confidentiality and data integrity. It transform our data into unintelligible form, data which we will be sending can be text or no text form, by encrypting our data we can save it from attacks like eavesdropping, in which interception of communication by unauthorized person, he can either listen or can add malicious information in our data which can lead to catastrophic results. This technique of secure data transmission is very useful in securing the integrity of data sent by the Unmanned Aerial Vehicles in military application to commercially used Electricity meter. Since the above mentioned devices uses microcontroller to send data through internet hence this data is always going to be susceptible to above mentioned threats so it is important to ensure that it doesn’t fall in wrong hands, our objective is that our microcontroller sends the data to remote location has authenticity, confidentiality and integrity. First we will send some meaningful text already stored in controller of STM3240G Eval-board then that data will be sent to server. These encrypted packets will be sending to remote server through Ethernet. At the receiver end this data will be received and decrypted to get the original captured data.
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Shivani Madhok,Gaurav Verma,Ankur Bhardwa j,Himanshu Verma,Ipsita Singh,Sushant Shekhar 보안공학연구지원센터 2015 International Journal of Bio-Science and Bio-Techn Vol.7 No.4
In this paper, we have designed an energy efficient wrist watch on 28nm FPGA. The code has been implemented in Xilinx ISE Design Suite 14.2. The device used is XC7K160T, package used is FBG676 and it is working on -3 speed grade. The wrist band will take the blood pressure as input and will tell about the state of the person wearing it. The design supports Internet of things service that’s why IP addresses are involved. This wrist band design is very helpful in biomedical areas. Research is in progress in this field. In this paper frequency is varied to obtain power consumption of Wrist Watch. Airflow has been kept 250 LFM and medium Heat sink. IO Standards has been varied in order to achieve an energy efficient device. Main emphasis has been done on MOBILE_DDR, LVTTL, HSUL_12, HSTL_I, LVCMOS33 and SSTL15 IO Standards. To design an energy efficient device we are using capacitance scaling and the capacitance is scaled down from 100pF to 20pF. During capacitance scaling, we observe that there is no change in clock power, logic power and signal power. Thermal Aware design is current research area. Analysis has been at two temperatures that is at 25 degree Celsius and at 50 degree Celsius. At the end we can conclude that the maximum power is consumed at 2.2GHz and minimum power is consumed at 1.2GHz. In respect of capacitance maximum power is consumed at 100pF and minimum power is consumed at 20pF at both temperatures at 25 degree Celsius and 50 degree Celsius.
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