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PLA에 의한 유한체 GF(2) 상의 비트 코드 연산 승산기의 구성
성현경 尙志大學校 生産技術硏究所 1999 生産技術論叢 Vol.7 No.-
In this paper, we are proposed the multiplication algorithm that multiply each bit to be encoded the bit code over the finite fields ??. This algorithm is shown the features as follows; 1) if the index ⅰ of Pⅰis larger than 0 and less than m-1, the coefficients Pⅰof the multiplication result polynomial is obtained the result to be added all values of (??)mod2 which ⅰ equals the value of j plus k, and 2) if the index ⅰ of Pⅰis larger than m and less than 2m-1, the coefficients Pⅰ of the multiplication result polynomial is obtained the result to be added all values of (??)mod2 which ⅰ equals the value of j plus k. This multiplier is constructed for 2≤m≤5 and is implemented in PLA. It is applied to the extension of degree m over ??.
窒素, 燐酸 및 加里의 施肥水準이 藥用作物 仙鶴草(Agrimonia pilosa L.)의 生育 및 收量에 미치는 影響
김현경,황필성,이용호,김기영,정대수 東亞大學校 大學院 2000 大學院論文集 Vol.25 No.-
This study was carried out to determine the effect of various fertilizer levels on the growth and yield of Agrimony. this experiment was conducted for 2years from 1998 to 1999 in Medicinal Plant Experiment Station, Kyungnam ARES. The results obtainned were summarized as follows : 1. The growth characteristics such as plant height, tillers and leaf numbers were more increased at 22-10-10 plot than of other fertilizer levels. 2. Variations of percent flowering of Agrimonia pilosa L. treated with different fertilizer levels were more increased at 22-10-10 plot than of other fertilizer levels. 3. Yield per 10a of Agrimonia pilosa L., Fresh weight was 1,500kg in 22-10-10 plot, and 243kg in non-treatment plot. The dry weight was 736kg in 22-10-10 plot, and 96kg in non-treatment plot. Yield of Seed and Fruit following to different application levels was highest at the fertilizing plot of N, P2O5, K2O=22-10-10.
Implementation of Ternary Adder and Multiplier Using Current-Mode CMOS
Hyeon-Kyeong Seong,Byeong-Ho Park,Sang-Ju Park,Dong-Young Park,Hong-Ki Min 대한전자공학회 2008 ICEIC:International Conference on Electronics, Inf Vol.1 No.1
In this paper, the ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS. Second, the ternary adder and multiplier over finite fields GF(3) are implemented to using the ternary T-gates based on current-mode CMOS. Finally, these circuits are simulated by Spice under 1.5 ㎂ CMOS standard technology with 15 μA unit current and 3.3V VDD voltage. The ratio of the width (W) and the length (L) in CMOS channel is 20 ㎛/2 ㎛. The simulated results are shown the satisfied current characteristics.
전류모드 CMOS에 의한 4치 가산기 및 승산기의 구현
성현경(Hyeon-Kyeong Seong) 한국정보기술학회 2014 한국정보기술학회논문지 Vol.12 No.1
In this paper, the quarternary adder and multiplier are implemented by current-mode CMOS. First, we implement the quarternary T-Gate using current-mode CMOS which has an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable quarternary addition table and multiplication table over finite fields GF(4) using the quarternary T-gates. We show the characteristics of operation for these circuits by HSpice simulation. These circuits are simulated by MOS model Level 47 Hspice under 0.18μm CMOS standard technology. The simulation results show the satisfying current characteristics. The simulation results of quarternary adder circuit and multiplier circuit using current-mode CMOS show the propagation delay time 0.12㎲, operating speed 300MHz, and consumer power 1.08mW The proposed circuits are reduced the number of transistor, and have a regularity of wiring and modularization, and are suitable for VLSI.
유한체 GF(3<SUP>m</SUP>)상의 고속 병렬 곱셈기의 설계
성현경(Hyeon-Kyeong Seong) 한국컴퓨터정보학회 2015 韓國컴퓨터情報學會論文誌 Vol.20 No.2
본 논문에서는 유한체 GF(3<SUP>m</SUP>)상에서 모든 항에 0이 아닌 계수를 갖는 기약 다항식에 대하여 m이 홀수 및 짝수인 경우 GF(3<SUP>m</SUP>)상의 곱셈 알고리즘을 제시하였으며, 제시한 곱셈 알고리즘을 이용하여 고속의 병렬 입-출력 모듈구조의 곱셈기를 설계하였다. 제시한 곱셈기의 구성은 (m+1)<SUP>2</SUP>개의 동일한 기본 셀들로 설계되었으며, 셀에 메모리를 사용하지 않았으므로 회로가 간단하며 셀당 TA+TX의 지연시간을 갖는다. 본 논문에서 제안한 곱셈기는 규칙성과 셀 배열에 의한 모듈성을 가지므로 m이 큰 회로의 확장이 용이하며 VLSI회로 실현에 적합할 것이다. In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields GF(3<SUP>m</SUP>), and design the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed (m+1)<SUP>2</SUP> same basic cells. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time TA+TX per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.
유한체 GF(p<SUP>m</SUP>)상의 고속 병렬 승산기의 설계
성현경(Hyeon-Kyeong Seong) 한국정보기술학회 2016 한국정보기술학회논문지 Vol.14 No.5
In this paper, we propose a new multiplicative algorithm of two polynomials for irreducible polynomial with all 1 of coefficients on finite fields GF(p<SUP>m</SUP>), and design the high-speed parallel multiplier on finite fields GF(p<SUP>m</SUP>) with input-output module structures using the proposed multiplicative algorithm. The presented high-speed parallel multiplier is designed the basic cells. Since the basic cells could not use a register circuit, the multiplier is very simple. The presented parallel multiplier is used m<SUP>2</SUP> addition gates and m<SUP>2</SUP> multiplication gates, and is short delay time T<SUB>A</SUB> + T<SUB>x</SUB> per cell unit. Total clock time is m unit time. Since the presented high-speed multiplier on finite fields GF(p<SUP>m</SUP>) have regularity and modularity by cell array, it is easy to extend the circuit with large m.
전류모드 CMOS에 의한 3치 가산기 및 승산기의 구현
성현경(Hyeon Kyeong Seong) 대한전기학회 2006 대한전기학회 학술대회 논문집 Vol.2006 No.10
In this paper, the Ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-gates. Finally, these operation circuits are simulated by Spice under 1.5㎛ CMOS standard technology, 15㎂ unit current. and 3.3V VDD voltage. The simulation results have shown the satisfying current characteristics. The ternary adder and multiplier implemented by current-mode CMOS are simple and regular for wire routing and possess the property of modularity with cell array.