http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
편평 사마귀의 한약치료에 대한 임상 연구 동향 - 중의학논문을 중심으로
성현경,김태연,Sung, Hyun Kyung,Kim, Tae Yeon 대한한방소아과학회 2016 대한한방소아과학회지 Vol.30 No.4
Objective The purpose of this study is to investigate recent clinical studies on the effect of herbal medicine in flat warts in China, and to seek better methods to treat and study for flat warts in Korea. Methods The clinical studies from the CAJ (China Academic Journal) of CNKI (China National Knowledge Infrastructure) by key words '扁平?' in recent 5 years (From January 2011 to December 2015) were searched. Results 16 articles were selected from 122 clinical studies, and analyzed. The most commonly used herbs were Isatidis Radix (板藍根), Equiseti Hiemalis Herba (木賊), Cyperi Rhizoma (香附子), Carthami Flos (紅花), Glycyrrhizae Radix (甘草) etc., and the articles all showed effectiveness over the control group. Conclusion Based on analyzing the studies, herbal medicine has shown effective in flat wart. This study may be useful not only as clinical data, but also to determine better treatment going forward.
전류모드 CMOS에 의한 4치 가산기 및 승산기의 구현
성현경 한국정보기술학회 2014 한국정보기술학회논문지 Vol. No.
본 논문에서는 전류모드 CMOS를 이용한 4치 가산기 및 승산기를 구현하였다. 먼저 효과적인 집적회로 설계 이용성을 갖는 전류모드 CMOS를 사용하여 4치 T-게이트를 구현하였다. 구현된 4치 T-게이트를 사용하여 유한체 GF(4)의 2변수 4치 가산표와 승산표를 실현하는 회로를 구현하였다. HSpice 시뮬레이션을 통하여 이 회로들에 대한 동작특성을 보였다. 구현된 회로들은 CMOS 표준 기술을 갖는 Hspice MOS 모델 LEVEL 47로 시뮬레이션 하였다. 본 논문에서 구현한 전류모드 CMOS에 의한 4치 가산기와 승산기의 시뮬레이션 결과에서 전달 지연시간이 이며, 4치 가산기와 승산기가 안정하게 동작하여 출력신호를 얻는 동작속도가 300MHz, 소비전력이 1.08mW임을 보였다. 제안된 회로는 트랜지스터의 감소와 회선경로의 규칙성, 모듈화가지며, VLSI화에 적합하다. In this paper, the quarternary adder and multiplier are implemented by current-mode CMOS. First, we implement the quarternary T-Gate using current-mode CMOS which has an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable quarternary addition table and multiplication table over finite fields GF(4) using the quarternary T-gates. We show the characteristics of operation for these circuits by HSpice simulation. These circuits are simulated by MOS model Level 47 Hspice under 0.18 CMOS standard technology. The simulation results show the satisfying current characteristics. The simulation results of quarternary adder circuit and multiplier circuit using current-mode CMOS show the propagation delay time 0.12㎲, operating speed 300MHz, and consumer power 1.08mW The proposed circuits are reduced the number of transistor, and have a regularity of wiring and modularization, and are suitable for VLSI.
컴퓨터 HDD의 LEAD ASSEMBLY 자동화 제조 설비의 설계
성현경 尙志大學校 生産技術硏究所 1997 生産技術論叢 Vol.- No.2
In this paper, we design the automatized manufacturing equipments for lead assembly that transmit data from the head of hard disk drive(HDD) to terminal board in computers. Since the diameter of raw wires is microscopic, it is very difficult to process the lead assembly manufacture manual work. Therefore, we design the step processing for manufacturing equipments of automatized lead assembly. The step processing has 4 step - cutting, stripping, twisting and tubing. The manufacturing equipments of automatized lead assembly designed here is the turn-table type. The turn-table device is rotated by torque of step motor and other devices are fixed. These equipments have an approximate 3 seconds per one products of lead assembly.