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CMOS Transistors with a 70-nm Gate Length for 0.13-μm-Node High-Performance Applications
Kyoung-Seok Rha,Dong-Hun Lee,Eun-Seung Jung,Hae-Kyung Kong,Hyae-Ryoung Lee,Jeong-Ho Lyu,Jeong-Hwan Yang,Jin-Suk Jung,Jung-A Choi,Kwang-Pyuk Suh,Young-Wug Kim 한국물리학회 2004 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.44 No.1
Conventional CMOS transistors for high performance with a 70-nm physical gate length were fabricated to evaluate the 130-nm-technology node. In this work, we enhanced the performance of transistors by using high-dose P+ implantation, a plasma-nitridation gas oxide, a hydrogen prebake (HPB), and a mechanical stress layer. We also reduced the overlap capacitances by using an oset spacer. The NMOS and PMOS have drive currents equal to 880 A/m and 420 A/m, respectively, with Ioff = 10 nA/m at Vdd = 1.2 V. The unit delay of the ring oscillator (1 fan-out) was 11.5 ps.