THEORY OF INFINITELY NEAR SINGULAR POINTS

Hironaka, Heisuke Korean Mathematical Society 2003 대한수학회지 Vol.40 No.5

The notion of infinitely near singular points, classical in the case of plane curves, has been generalized to higher dimensions in my earlier articles ([5], [6], [7]). There, some basic techniques were developed, notably the three technical theorems which were Differentiation Theorem, Numerical Exponent Theorem and Ambient Reduction Theorem [7]. In this paper, using those results, we will prove the Finite Presentation Theorem, which the auther believes is the first of the most important milestones in the general theory of infinitely near singular points. The presentation is in terms of a finitely generated graded algebra which describes the total aggregate of the trees of infinitely near singular points. The totality is a priori very complex and intricate, including all possible successions of permissible blowing-ups toward the reduction of singularities. The theorem will be proven for singular data on an ambient algebraic shceme, regular and of finite type over any perfect field of any characteristics. Very interesting but not yet apparent connections are expected with many such works as ([1], [8]).

The Challenges of Managing Cross-Cultural Employees of Japanese Manufacturing SMEs in Malaysia: Raising Employees’ Learning Consciousness

( Chikako Hironaka ),( Asako Terazawa ) 한국중소기업학회 2019 기업가정신과 벤처연구 Vol.22 No.3

Management of cross-cultural employees of Japanese manufacturing small and medium- sized enterprises (SMEs) in Malaysia is the subject of the present study. In particular, this study focuses on raising local employees’ learning consciousness and sheds light on the effect of communication and organizational culture. Learning is a distinctive feature of Japanese companies. In Malaysia, however, Japanese SMEs are struggling to maintain their culture of learning. An empirical survey on learning was conducted with the local employees in our study. First, the survey results highlighted the importance of communication. Japanese SMEs can overcome the language and cultural barriers by effective frequent communication. Clarity on the job, on issues such as current responsibilities, rewards, and promotions, is critical to raising learning consciousness. Second, the study also focuses on the role of Japanese management culture. Japanese companies exemplify learning behavior and the present study clarifies how this unique culture increases employees’ affection and raises learning consciousness. The study provides evidence that affective commitment alone is not sufficient to boost learning consciousness. The study results also have important implications to the practitioner.

Theory of infinitely near singular points

Heisuke Hironaka 대한수학회 2003 대한수학회지 Vol.40 No.5

The notion of infinitely near singular points, classical in the case of plane curves, has been generalized to higher dimensions in my earlier articles (\cite{hiro:garden}, \cite{hiro:intromadrid}, \cite{hiro:idealexpo}). There, some basic techniques were developed, notably the three technical theorems which were \emph{ Differentiation Theorem}, \emph{Numerical Exponent Theorem} and \emph{Ambient Reduction Theorem} \cite{hiro:idealexpo}. In this paper, using those results, we will prove the \emph{Finite Presentation Theorem}, which the auther believes is the first of the most important milestones in the general theory of infinitely near singular points. The presentation is in terms of a \emph{finitely generated} graded algebra which describes the total aggregate of the trees of infinitely near singular points. The totality is a priori very complex and intricate, including all possible successions of permissible blowing-ups toward the reduction of singularities. The theorem will be proven for singular data on an ambient algebraic shceme, regular and of finite type over any perfect field of any characteristics. Very interesting but not yet apparent connections are expected with many such works as (\cite{abhy:planecurve}, \cite{yous:newtonpoly}).

Glioblastoma Multiforme in the Pineal Region with Leptomeningeal Dissemination and Lumbar Metastasis

Matsuda, Ryosuke,Hironaka, Yasuo,Suigimoto, Tadashi,Nakase, Hiroyuki The Korean Neurosurgical Society 2015 Journal of Korean neurosurgical society Vol.58 No.5

We report a case of a 31-year-old woman with glioblastoma multiforme (GBM) in the pineal region with associated leptomeningeal dissemination and lumbar metastasis. The patient presented with severe headache and vomiting. Magnetic resonance imaging (MRI) of the brain showed a heterogeneously enhanced tumor in the pineal region with obstructive hydrocephalus. After an urgent ventricular-peritoneal shunt, she was treated by subtotal resection and chemotherapy concomitant with radiotherapy. Two months after surgery, MRI showed no changes in the residual tumor but leptomeningeal dissemination surrounding the brainstem. One month later, she exhibited severe lumbago and bilateral leg pain. Thoracico-lumbar MRI showed drop like metastasis in the lumbar region. Finally she died five months after the initial diagnosis. Neurosurgeons should pay attention to GBM in the pineal region, not only as an important differential diagnosis among the pineal tumors, but due to the aggressive features of leptomeningeal dissemination and spinal metastasis.

Proposition and Evaluation of a Bank based Multi-port Memory with Blocking Network

Tomohiro Inoue,Tetsuo Hironaka,Takahiro Sasaki,Seiji Fukae,Tetsushi Koide,Hans Juurgen Mattausch 대한전자공학회 2004 ITC-CSCC :International Technical Conference on Ci Vol.2004 No.7

OS Functions for a Distributed FPGA Cluster System

KOJIMA Akira,TOKUNAGA Kazuya,HIRONAKA Tetsuo 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7

In reconfigurable computer systems that have reconfigurable resources like FPGA, CPLD etc., OS functions will be necessary to improve utilization of the systems. We have been studying OS functions for these reconfigurable systems. Our first target hardware was tightly coupled FPGA cluster using shared bus and it is easy to access reconfigurable resources, but it is difficult to increase the number of resources. Our second target system is distributed FPGA cluster that is connected by network and it is easy to increase the number of reconfigurable resources, but complicated network handling is necessary to communicate between host computer and reconfigurable resources. In this paper, OS functions for the distributed FPGA cluster system are described, which provide communication services and have compatible simple programming interface with the first target hardware.

Development and Evaluation of Raytracing Accelerating Engine with Bit Serial Arithmetic Units

Tomoyuki Kawamoto,Kazuya Tanigawa,Tetsuo Hironaka,Yuhki Yamabe 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7

In recent years, development of various rendering algorithm provide photorealistic image. However, requirement of quality for rendering causes significant increase of processing time. Raytracing method can generate high quality images.But, it needs much time to get images. Several methods of parallel computing for high speed processing for raytracing with hardware are discussed. But, the chip of conventional raytracing hardware needs huge area because of parallel arithmetic units on it , which result in difficulty on inserting more processing elements(PEs) into the chip. In this paper, we present hardware design of a raytracing accelerator engine with bit serial arithmetic unit to improve performance. Area of bit serial arithmetic unit is small, and operation performance per the unit area is high. We adopt a dot mode for parallel processing because it can make maximum use of the characteristic of bit serial(BS) arithmetic unit. As the first stage, we design prototype hardware which calculate only the process of highest load ratio in PE, and evaluate it. As a result, prototype hardware is about 5.09 times faster on processing time.

Development of DS-HIE Architecture

Tetsuya Zuyama,Kazuya Tanigawa,Tetsuo Hironaka 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7

In this paper, we propose DS-HIE architecture as a dynamic reconfigurable architecture which has the policy to decrease the necessity of dynamic reconfiguration as much as possible. In the proposed architecture we introduce digit-serial operation to increase the de㎱ity of the operation units per area and to reduce necessary reconfiguration. In addition, to achieve small area size and high flexibility on routing, we adopted benes network for its routing resource. We synthesized DS-HIE-α processor designed as a prototype processor with HITACHI 0.18㎛ standard cell library by Synopsys Design Compiler. As a result, the tra㎱istor count of DS-HIE-α processor with 250㎒ was 1.99MTr, and the execution time of 2-dime㎱ional DCT was 1088㎱. The tra㎱istor count of it with 500㎒ was 2.44MTr, and the execution time of 2-dime㎱ional DCT was 544㎱. In addition, the tra㎱istor count of Pentium4 (Northwood 3.2㎓) implemented by 0.13㎛ process was 178MTr, and the execution time of 2-dime㎱ional DCT was 660㎱. As compared with Pentium4, DS-HIE-α processor with 500㎒ achieves almost equal performance, while it was implemented with an extremely smaller tra㎱istor count.

Synthesis and structure of stable 1,2-diaryldisilyne

Sasamori, Takahiro,Han, Joon Soo,Hironaka, Koji,Takagi, Nozomi,Nagase, Shigeru,Tokitoh, Norihiro De Gruyter 2010 Pure and Applied Chemistry Vol.82 No.3

<P>A novel 1,2-diaryldisilyne, BbtSi≡SiBbt (Bbt = 2,6-bis[bis(trimethylsilyl)methyl]-4-[tris(trimethylsilyl)methyl]phenyl), was synthesized as a stable compound by reduction of the corresponding 1,2-dibromodisilene, Bbt(Br)Si=Si(Br)Bbt. The spectral and structural features of this first stable 1,2-diaryldisilyne are revealed, and the Si≡Si triple-bond character is evaluated with the aid of detailed theoretical calculations. The triple-bond characters of BbtSi≡SiBbt and BbtGe≡GeBbt are compared based on experimental and theoretical results.</P>

Development and Implementation of OS Functions for a Computer System Having FPGA Devices as Reconfigurable Resources

Kazuya Tokunaga,Akira Kojima,Tetsuo Hironaka 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7

Many researchers and companies have been interested in computer systems which have reconfigurable devices as programmable resources. Current Reconfigurable systems (RC systems) are basically single task systems, but the number of reconfigurable devices in these systems has increased so that multitasking environment for the systems are required to use the devices efficiently. In this paper, we develop the OS functions to support executing user programs which use FPGAs as customized hardware in multitasking environment. The target system consists of a host compute and FPGAs. The functions are implemented on the target system as RCOS server. RC-OS server supports management of FPGA resources and communication control between host computer and FPGA resources. We develop the programs which use the RC-OS functions, and executed them in multitasking environment on our prototype RC system. As the result, it shows that RC-OS server improves the usability of target system.