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Development of DS-HIE Architecture
Tetsuya Zuyama,Kazuya Tanigawa,Tetsuo Hironaka 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
In this paper, we propose DS-HIE architecture as a dynamic reconfigurable architecture which has the policy to decrease the necessity of dynamic reconfiguration as much as possible. In the proposed architecture we introduce digit-serial operation to increase the de㎱ity of the operation units per area and to reduce necessary reconfiguration. In addition, to achieve small area size and high flexibility on routing, we adopted benes network for its routing resource. We synthesized DS-HIE-α processor designed as a prototype processor with HITACHI 0.18㎛ standard cell library by Synopsys Design Compiler. As a result, the tra㎱istor count of DS-HIE-α processor with 250㎒ was 1.99MTr, and the execution time of 2-dime㎱ional DCT was 1088㎱. The tra㎱istor count of it with 500㎒ was 2.44MTr, and the execution time of 2-dime㎱ional DCT was 544㎱. In addition, the tra㎱istor count of Pentium4 (Northwood 3.2㎓) implemented by 0.13㎛ process was 178MTr, and the execution time of 2-dime㎱ional DCT was 660㎱. As compared with Pentium4, DS-HIE-α processor with 500㎒ achieves almost equal performance, while it was implemented with an extremely smaller tra㎱istor count.
Development and Evaluation of Raytracing Accelerating Engine with Bit Serial Arithmetic Units
Tomoyuki Kawamoto,Kazuya Tanigawa,Tetsuo Hironaka,Yuhki Yamabe 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
In recent years, development of various rendering algorithm provide photorealistic image. However, requirement of quality for rendering causes significant increase of processing time. Raytracing method can generate high quality images.But, it needs much time to get images. Several methods of parallel computing for high speed processing for raytracing with hardware are discussed. But, the chip of conventional raytracing hardware needs huge area because of parallel arithmetic units on it , which result in difficulty on inserting more processing elements(PEs) into the chip. In this paper, we present hardware design of a raytracing accelerator engine with bit serial arithmetic unit to improve performance. Area of bit serial arithmetic unit is small, and operation performance per the unit area is high. We adopt a dot mode for parallel processing because it can make maximum use of the characteristic of bit serial(BS) arithmetic unit. As the first stage, we design prototype hardware which calculate only the process of highest load ratio in PE, and evaluate it. As a result, prototype hardware is about 5.09 times faster on processing time.
Keisuke Yamamoto,Kazuya Tanigawa,Tetsuo Hironaka,Takashi Ishiguro 대한전자공학회 2015 ITC-CSCC :International Technical Conference on Ci Vol.2015 No.6
A memory based PLD (MPLD) has been proposed as one of reconfigurable device. A MPLD consists of multiple-output look-up tables (MLUTs) which is reconfigurable element diagonally connected by AD pairs. MPLD can improve routing ability among logic elements by increasing the number of AD pairs. However, there is problem that chip area of MLUT will be doubled by each additional AD pairs. On the other hand, if a MLUT with fewer number of AD pairs is used for small chip area, it decreases logic density since many MLUTs are used as a part of routing resources. To solve the problem, we propose a small logic element while keeping routing ability high, compared with MLUT. We adopted selector-based logic element to decrease chip area. From the estimation results in this paper, we found that the number of transistor counts required to implement our proposed logic element is decreased to 18.7 % of transistor counts, compared with MLUT with six AD pairs.
Design Consideration of a Secure Sensor Chip for Home Cancer Examination
Tomohiro Tanaka,Kazuya Tanigawa,Tetsuo Hironaka,Takashi Ishiguro 대한전자공학회 2015 ITC-CSCC :International Technical Conference on Ci Vol.2015 No.6
We propose a secure sensor chip for disposable medical examination for home use. Secure sensor chip is required to have functions for encryption and authentication to prevent personal information leakage. In this paper, we estimated secure sensor chip implementations by specific hardware and micro-controller respectively. As a result, the implementation of specific hardware is 40% of chip area in terms of NAND gates, compared with the micro-controller one.
Yasuhiro NISHINAGA,Takuro UCHIDA,Tetsuya ZUYAMA,Kazuya TANIGAWA,Tetsuo HIRONAKA 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
We have developed the dynamic reconfigurable processor DS-HIE for the streaming processing in our laboratory. The software development environment for the DS-HIE processor was not developed. So it is difficult to evaluate the performance of the DS-HIE processor by using practical applications. Therefore, this paper explains about the development of the compiler for the DS-HIE processor, which supports high-level programming language. The compiler consists of the Front-end part and the Back-end part. Since it will take time to develop a high quality Front-end from the scratch, so we selected the COINS compiler as the Front-end compiler. The Back-end compiler extracts the parts executed by the DS-HIE processor in the input program, and then maps the operations to the Function Units in the DS-HIE processor. After that, the Back-end compiler routes wires between the Function Units. The applications to evaluate the compiler were one dimensional DCT and row processing of LDCP decoding. As a compilation result, the average usage of the function unit was 83%
Development of Heterogenous Multi-core Processor ”Hy-DiSC” with Dynamic Reconfigurable Processor
Takuro UCHIDA,Yasuhiro NISHINAGA,Tetsuya ZUYAMA,Kazuya TANIGAWA,Tetsuo HIRONAKA 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
For accelerating multimedia applications by streaming, we have proposed the heterogeneous multicore processor Hy-DiSC with dynamic reconfigurable processor DS-HIE. The goal of the Hy-DiSC processor is to achieve high performance in a small chip area. In this paper, the performance improvement of the Hy-DiSC processor adopting the DS-HIE processor was evaluated. The application programs that selected for performance evaluation was a JPEG encoding process and the 2-D DCT included in the JPEG encoding process. And, the DS-HIE processor accelerates the 2-D DCT included in the JPEG encoding process. As a result, compared with the MeP processor the DS-HIE processor achieved 28 times higher performance on the execution of 2-D DCT. And, the DS-HIE processor requires fewer transistor counts to implement it.
Low Cost PLD with High Speed Partial Reconfiguration
Naoki Hirakawa,Masanori Yoshihara,Masayuki Sato,Kazuya Tanigawa,Tetsuo Hironaka 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
Recently, Field Programmable Gate Arrays (FPGAs) have been used for implementing various types of logic functions. But the conventional FPGAs have the following problems. The conventional FPGAs include switch matrixes for programmable connection, but the switch matrix occupies a significantly large area of the FPGA. As another problem, the configuration speed is slow because of the serial configuration method. To resolve these problems, we proposed MPLD as a new Programmable Logic Device (PLD) architecture which introduce MLUT instead of the conventional LUT. In MPLD each MLUT can be used as a combination logic, memory and switch matrix, on the demand of the mapped circuit. The merits of MPLD are the following. 1) MPLD can behave as both the reconfigurable device and the conventional parallel memory. 2) Implementing cost of MPLD is cheaper than the conventional FPGAs, because MPLD does not need switch matrixes as the conventional FPGA does. 3) The configuration speed is fast and partial configuration is easy because configuration method of MPLD is same as write access of the conventional parallel memory. In this paper, we present the MPLD architecture and its evaluation results of the prototype MPLD chip.