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- 저자 : Tetsuya Zuyama (검색결과 3 건)
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Development of DS-HIE Architecture
Tetsuya Zuyama,Kazuya Tanigawa,Tetsuo Hironaka 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
In this paper, we propose DS-HIE architecture as a dynamic reconfigurable architecture which has the policy to decrease the necessity of dynamic reconfiguration as much as possible. In the proposed architecture we introduce digit-serial operation to increase the de㎱ity of the operation units per area and to reduce necessary reconfiguration. In addition, to achieve small area size and high flexibility on routing, we adopted benes network for its routing resource. We synthesized DS-HIE-α processor designed as a prototype processor with HITACHI 0.18㎛ standard cell library by Synopsys Design Compiler. As a result, the tra㎱istor count of DS-HIE-α processor with 250㎒ was 1.99MTr, and the execution time of 2-dime㎱ional DCT was 1088㎱. The tra㎱istor count of it with 500㎒ was 2.44MTr, and the execution time of 2-dime㎱ional DCT was 544㎱. In addition, the tra㎱istor count of Pentium4 (Northwood 3.2㎓) implemented by 0.13㎛ process was 178MTr, and the execution time of 2-dime㎱ional DCT was 660㎱. As compared with Pentium4, DS-HIE-α processor with 500㎒ achieves almost equal performance, while it was implemented with an extremely smaller tra㎱istor count.
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Yasuhiro NISHINAGA,Takuro UCHIDA,Tetsuya ZUYAMA,Kazuya TANIGAWA,Tetsuo HIRONAKA 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
We have developed the dynamic reconfigurable processor DS-HIE for the streaming processing in our laboratory. The software development environment for the DS-HIE processor was not developed. So it is difficult to evaluate the performance of the DS-HIE processor by using practical applications. Therefore, this paper explains about the development of the compiler for the DS-HIE processor, which supports high-level programming language. The compiler consists of the Front-end part and the Back-end part. Since it will take time to develop a high quality Front-end from the scratch, so we selected the COINS compiler as the Front-end compiler. The Back-end compiler extracts the parts executed by the DS-HIE processor in the input program, and then maps the operations to the Function Units in the DS-HIE processor. After that, the Back-end compiler routes wires between the Function Units. The applications to evaluate the compiler were one dimensional DCT and row processing of LDCP decoding. As a compilation result, the average usage of the function unit was 83%
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Development of Heterogenous Multi-core Processor ”Hy-DiSC” with Dynamic Reconfigurable Processor
Takuro UCHIDA,Yasuhiro NISHINAGA,Tetsuya ZUYAMA,Kazuya TANIGAWA,Tetsuo HIRONAKA 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
For accelerating multimedia applications by streaming, we have proposed the heterogeneous multicore processor Hy-DiSC with dynamic reconfigurable processor DS-HIE. The goal of the Hy-DiSC processor is to achieve high performance in a small chip area. In this paper, the performance improvement of the Hy-DiSC processor adopting the DS-HIE processor was evaluated. The application programs that selected for performance evaluation was a JPEG encoding process and the 2-D DCT included in the JPEG encoding process. And, the DS-HIE processor accelerates the 2-D DCT included in the JPEG encoding process. As a result, compared with the MeP processor the DS-HIE processor achieved 28 times higher performance on the execution of 2-D DCT. And, the DS-HIE processor requires fewer transistor counts to implement it.
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