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      • Development and Evaluation of Raytracing Accelerating Engine with Bit Serial Arithmetic Units

        Tomoyuki Kawamoto,Kazuya Tanigawa,Tetsuo Hironaka,Yuhki Yamabe 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7

        In recent years, development of various rendering algorithm provide photorealistic image. However, requirement of quality for rendering causes significant increase of processing time. Raytracing method can generate high quality images.But, it needs much time to get images. Several methods of parallel computing for high speed processing for raytracing with hardware are discussed. But, the chip of conventional raytracing hardware needs huge area because of parallel arithmetic units on it , which result in difficulty on inserting more processing elements(PEs) into the chip. In this paper, we present hardware design of a raytracing accelerator engine with bit serial arithmetic unit to improve performance. Area of bit serial arithmetic unit is small, and operation performance per the unit area is high. We adopt a dot mode for parallel processing because it can make maximum use of the characteristic of bit serial(BS) arithmetic unit. As the first stage, we design prototype hardware which calculate only the process of highest load ratio in PE, and evaluate it. As a result, prototype hardware is about 5.09 times faster on processing time.

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