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Jun, Jaehoon,Rhee, Cyuyeol,Kim, Sangwoo,Kim, Suhwan IEEE 2017 IEEE SENSORS JOURNAL Vol.17 No.17
<P>This paper presents a switched capacitor interface circuit for a monolithic three-axis capacitive micro-electromechanical system (MEMS) accelerometer. The MEMS sensor and the interface circuit of our system-in-package-type MEMS accelerometer are 3-D stacked to optimize integration density with a small package footprint. The proposed fully integrated interface circuit includes a capacitance-to-voltage converter followed by a Delta Sigma analog-to-digital converter (ADC). To optimize system power and area, the programmable-gain functionality is embedded to the second-order Delta Sigma ADC without any stability degradation. The offset and 1/f noise of the fully differential interface circuit are mitigated by a correlated double sampling technique. The rest of the low-frequency error from system mismatch is also suppressed by calibration using fine metaloxide-semiconductor capacitor array. The measurement results of our MEMS accelerometer show a 13.7-b maximum effective resolution with the 197-mu g/ root Hz noise floor in a conversion time of 1 ms with a maximum nonlinearity of 1.09%. Implemented in a standard 0.18-mu m CMOS technology, the fabricated chip consumes only 247-mu A current from a 3.3-V supply, and 37-mu A current from a 1.8-V supply.</P>
A Sub-1.0-V On-Chip CMOS Thermometer With a Folded Temperature Sensor for Low-Power Mobile DRAM
Hyunjoong Lee,Daeyong Shim,Cyuyeol Rhee,Mino Kim,Suhwan Kim IEEE 2016 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.63 No.6
<P>As Dynamic Random Access Memory (DRAM) supply voltages drop below 1 V with the scaling down of the process, it becomes increasingly difficult to construct a temperature sensor with sufficient accuracy to control self-refresh, without occupying significant area or consuming increased power. In this brief, we propose an on-chip CMOS thermometer with a temperature sensor, the output of which is divided into segments by a folding scheme. The slopes of these segments can be arranged to be the same or adjusted separately, as desired for the output. Implemented in a 29-nm DRAM process, the sensor operates from -40 degrees C to 95 degrees C at the supply voltage of 0.8 V, with a temperature sensitivity of -3.1 mV/degrees C between -40 degrees C and 35 degrees C, and -2.1 mV/degrees C between 35 degrees C and 95 degrees C. It has an area of 0.0016 mm(2) and consumes less than 0.144 mu W.</P>
Daeyong Shim,Hyunsik Jeong,Hyunjoong Lee,Cyuyeol Rhee,Deog-Kyoon Jeong,Suhwan Kim IEEE 2013 IEEE journal of solid-state circuits Vol.48 No.10
<P>Smaller transistors mean that capacitors are charged less uniformly, which increases the self-refresh current in the DRAMs used in mobile devices. Adaptive self-refresh using an on-chip thermometer can solve this problem. We propose an on-chip CMOS thermometer specifically designed for controlling the refresh period of a DRAM. This thermometer includes a novel temperature sensor which has been implemented and integrated into an LPDDR2 chip. The LPDDR2 chip is fabricated in a 44-nm DRAM process. The sensor has a temperature sensitivity of -3.2 mV/°C, over a range of 0°C to 110°C. Its resolution is 1.94°C and is only limited by the 6.2-mV step of the associated resistor ladder not by its own design. The linearity of the sensor permits one-point calibration, after which the errors in 61 sample circuits ranged between -1.42°C and +2.66°C. The sensor has an active area of 0.001725 mm<SUP>2</SUP> and consumes less than 0.36 μW on average with a supply of 1.1 V. At its lowest operating temperature, this thermometer reduces the IDD6 current of the LPDDR2 chip by almost half.</P>