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한석붕,김강철,백한석 대한전자공학회 2006 電子工學會論文誌-SD (Semiconductor and devices) Vol.43 No.5
In this paper, a new testing technique for core components of wireless transceiver was proposed. That was, band fault models (including the information of specifications in the analogue and RF IC) and methods which can test specifications in the time domain easily by observing a variation of band fault models in the circuit output were proposed and developed. This technique had an advantage over testing technique in frequency domain because it didn't need expensive test equipments and could reduce the time required. Test technique proposed in this paper was adapted to the test of 5.25 GHz low noise amplifier and proved that this testing technique was efficient in RF IC including low noise amplifier. 본 논문에서는 무선 트랜시버 구성소자들의 완제품 테스팅을 용이하게 할 수 있는 새로운 테스팅 기법을 제안하였다. 즉, RF 집적회로에 존재하는 고장들에 대하여 설계사양의 정보를 포함하는 구간고장모델(band fault model)을 제안하고 이 구간고장모델들의 변화를 회로의 출력에서 그대로 관찰할 수 있도록 함으로써 시간영역에서 설계사양에 대한 테스트를 용이하게 할 수 있는 방식을 제시하였다. 이 방식은 주파수 영역에서 테스트를 행하는 기존의 설계사양 테스트를 시간영역에서 용이하게 테스트할 수 있도록 함으로써 고가의 테스트 장비가 필요 없으며 테스트 시간이 단축되는 장점이 있다. 본 논문에서 제시된 테스팅 기법을 5.25 GHz 저잡음증폭기의 테스트에 적용하여 설계사양을 고려한 시간영역 테스팅 기법이 저잡음증폭기를 비롯한 RF 집적회로의 테스트에 매우 효과적임을 입증하였다.
韓晳鵬 慶尙大學校 1989 論文集 Vol.28 No.2
This paper proposes a testable design and testing method for NORA CMOS circuits. In the design method, feedback loops are formed in NORA CMOS circuits by adding simple extra circuits. In test mode, the oscillation occurs through the feedback loops and can be observed at the primary output. By this method, test generation, test pattern application and test data evaluation can be done esaily. Especially, the multiple faults which are not detected by the conventional testing method can be detected, the fault-free response for each test pattern need not to be predetermined. In case the conventional testing method is applied to the sequential NORA(NO RAce) CMOS circuits with the LSSD(Level Sensitive Scan Design) design technique, it is confronted with the serious problems that the initial value . By using the proposed design method, however, the sequential NORA CMOS circuits with the LSSD design technique can be easily tested without such problems. The validity of the proposed design method is verified by the circuit level simulation(SPICE 2G.6) and logic level simulation(HILO-3)
Test 용역성을 고려한 LSI/VLSI 논리설계방식과 Programmable Logic Array에의 응용
한석붕,조상복,임인칠,Han, Seok-Bung,Jo, Sang-Bok,Im, In-Chil 대한전자공학회 1984 전자공학회지 Vol.21 No.3
논문에서는 종래의 LSSD에 사용한 쉬프트 레지스터 래치를 개선한 새로운 LSI/VLSI 논리설계방식을 제안한다. 이 설계방식을 사용함으로써 테스트 패턴의 생성이 용이해지고 고장검출률이 향상된다. 또한 여기서 제안한 병렬 쉬프트 레지스터 래치를 테스트가 용이한 PLA의 설계에 적용한다. 이 경우에 테스트 패턴의 수가 감소되고 LSSD를 사용한 종래의 PLA에서 귀환입력에 변가되는decoder가 제거된다. This paper proposes a new LSI/VLSI logic design structure which improves shift register latches in conventional LSSD. Test patterns are easily generated and fault coverage is enhanced by using the design structure. The new parallel shift register latch can be applied to the design of easily testable PLA's. In this case, the number of test patterns is decreased and decoders which are added to the feedback inputs in conventional PLA's using LSSD are not necessary.
이효상,송근호,김강철,한석붕 慶尙大學校 工科大學 自動化및컴퓨터應用技術硏究所 1995 自動化 및 컴퓨터應用技術 Vol.2 No.1
This paper proposes a testing method which can detect the bridging faults of CLA adder designed by ENMODL in transistor level. It is a application of IDDQ testing method. In conventional dynamic CMOS, no current flows through CMOS clocking device in spite of the fault in the function block. But in ENMODL CMOS, the current flows through the second level, which is the enhanced structure by the application of the proper test pattern. The possibility of testing is verified by SPICE 3 simulation.
CMOS VLSI의 IDDQ 테스팅을 위한 간략한 테스트 패턴 생성
송근호,김영일,이건기,한석붕 慶尙大學校 工科大學 自動化및컴퓨터應用技術硏究所 1996 自動化 및 컴퓨터應用技術 Vol.3 No.1
This paper proposes a new dynamic compaction algorithm, which is applied to IDDQ testing for intra-gate bridging faults in CMOS VLSI. The proposed algorithm generates a test pattern for a target fault, then χ_gates are selected to detect additional faults. Backtrace using random and four methods of controllability are rotated to get a further reduced test set. Experimental results for ISCAS'85 benchmark circuits showed that close-to-minimum test sets were obtained by the proposed algorithm.
내부 전류 테스팅을 위한 내장형 전류감지기의 설계 및 구현
송근호,방만식,이효상,서정훈,김강철,한석붕 慶尙大學校 工科大學 自動化및컴퓨터應用技術硏究所 1997 自動化 및 컴퓨터應用技術 Vol.4 No.1
This paper proposes a new BIC(Built-in Current sensor) for the internal current test in CMOS logic circuits. Our BIC is composed of current sensor, level shifter, comparator, and reference voltage circuit. The current sensor parallel connected with one diode and one nMOS device can convert the current of CUT(Circuit Under Test) to voltage. A single phase clock is employed in the BIC reduce the control circuitry of it and to perform a self-testing for a faulty current. The proposed BIC is verified by using the HSPICE simulator and fabricated in 0.8 ㎛ twin-tub process. The CUT is 4 bit full adder with bridging faults. The realized BIC successfully detects all bridging faults in CUT.