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진주환 ( Ju Hwan Jin ),길기정 ( Ki Jung Kil ),이영종 ( Young Jong Lee ) 대한본초학회 2004 大韓本草學會誌 Vol.19 No.2
N/A Objective : Allii Tuberosi Semen and Allii Fistulosi Semen have been sold mixed with fabricated forms of them in Korea. hn such a situation, seeds of Allium tuberosum Rottler, A. fistulosum Linne, and A. cepa Linne were collected and their external, internal, and flour states were observed through microscopic examination. Method : The slice of the tested material made by paraffin section technique was colored with Safranine Malachite Green contrast methods, and the flour of it was mounted by the liquid made by the same ratio of each of glycerin, acetic acid, and water, and then observed and photographed by olymphus-BHT. Result 1. Allii Tuberosi Semen showed the salient network-like wrinkles on its upper side, but Allii Fistulosi Semen and Allii Cepae Semen had 1 -2 lines on their upper sides. 2. The length of Allii Cepae Semen was 2.5?3.5mm, and the width of it was 1.5--2.5mm, which was a bit small; but the length of Allii Fistulosi Semen was 3-4mm, and the width of it was 2?3mm, which was a bit large. 3. In the flour forms, Allii Tuberosi Semen has network-like pattern in the surface of the seed coat epidermal cell wall, but Allii Fistulosi Semen and Allii Cepae Semen have litte or no such pattern. Conclusion : Because there are some clear differences in external and flour states of Allii Tuberosi Semen. Allii Fistulosi Semen, and Allii Cepae Semen, microscopic examination can be used to distinghish them and their fake forms in flour states.
센서 애플리케이션을 위한 이득 조정 있는 저전력 3차 델타 시그마 아날로그 디지털 변환기
진주환(Joohwan Jin),채형일(Hyungil Chae) 대한전자공학회 2021 전자공학회논문지 Vol.58 No.11
본 논문에서는 저전력 동작 및 이득 조정(Gain Calibration)을 가진 3차 저전력 Delta-Sigma 아날로그-디지털 변환기를 설계하였다. 3차 Delta-Sigma 아날로그-디지털 변환기를 구성하며, 저전력 구동을 위하여 Inverter based Amplifier를 사용한다. 또한, 저전력 동작을 위해 Double Sampling 기법을 사용하여 같은 Sampling rate에서 더 높은 전력 효율을 얻는다. Inverter based Amplifier는 PVT Variation과 Input의 Common mode Voltage Variation에 민감하므로 이득 조정과 LDO(Low Drop-Out regulator), CMFB(Common Mode Feedback) 회로를 추가하여 이러한 문제를 해결한다. 제안하는 회로는 180nm CMOS 공정으로 구현했다. PSD(Power Spectrum Density)그래프 결과 SNDR은 77.45 dB가 측정되었고 ENOB은 12.57 bit, 전체 전력 소모는 27.92 uW인 것을 확인했다. In this paper, a third-order low-power Delta-Sigma Analog-to-Digital Converter with low-power operation and Gain Calibration is designed. A 3rd order Delta-Sigma Analog-to-Digital Converter is constructed, and an Inverter based Amplifier is used for low power operation. In addition, higher power efficiency is obtained at the same Sampling rate by using the Double Sampling technique for low-power operation. Inverter based Amplifier is sensitive to PVT Variation and Common mode Voltage Variation of Input, so it solves this problem by adding Gain Calibration, LDO (Low Drop-Out regulator) and CMFB (Common Mode Feedback) circuit. The proposed circuit was implemented in a 180nm CMOS process. As a result of the PSD (Power Spectrum Density) graph, it was confirmed that SNDR was measured at 77.45 dB, ENOB was 12.57 bit, and total power consumption was 27.92 uW.