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이은선,이동화,정현우,임성훈,이상렬,Lee, Eun-Sun,Li, Dong-Hua,Chung, Hyun-Woo,Lim, Sung-Hoon,Lee, Sang-Yeol 한국전기전자재료학회 2005 전기전자재료학회논문지 Vol.18 No.4
Pb(Zr/sub 0.52/Ti/sub 0.48/)O₃(PZT) thin films were deposited by using a pulsed laser deposition method on a Pt/Ti/SiO₂/Si substrate with (Pb/sub 0.72/La/sub 0.28/)Ti/sub 0.93/O₃ (PLT) buffer and on a Pt/Ti/SiO₂/Si substrate without buffer. These films were annealed in H₂-contained ambient for 30 minutes at the substrate temperature of 400。C to evaluate the forming gas annealing effects. The comparative studies on the ferroelectric properties of these two films were carried out, which are shown that ferroelectric properties, such as remanent polarization didn't change in the case of PLT buffered PZT film while remanent polarization value of PZT film degraded from 20.8 C/㎠ to 7.3 C/㎠. The leakage current became higher in both cases, but that of the more-oriented PZT film had the moderate value of the 10/sup -6/ order of A/㎠. This is mainly because the hydrogen atoms which make the degradation of PZT films cannot infiltrate into the more -oriented PZT film as well as the less-oriented PZT film.
2-bit/cell Folded Split Gate Flash Memory의 제작 방법
박세환(Se Hwan Park),박일한(Il Han Park),조성재(SeongJae Cho),윤장근(Jang-Gn Yun),이정훈(Jung Hoon Lee),이동화(Dong Hua Li),김두현(Doo-Hyun Kim),이길성(Gil Sung Lee),김윤(Yoon Kim),이종덕(Jong Duk Lee),박병국(Byung-Gook Park) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
A new 2-bit/cell SONOS flash memory device is designed. The device has recessed channel and a supplementary gate named as a select gate. The designed structure looks like a folded form of conventional one, so we call the device Folded Split Gate (FSG) flash memory
SOI 기판 상에 구현된 플래시 메모리의 구현 조건에 대한 프로그램 동작 효율의 의존성
조성재(Seongjae Cho),박일한(Il Han Park),이정훈(Jung Hoon Lee),윤장근(Jang-Gn Yun),김두현(Doo-Hyun Kim),이길성(Gil Sung Lee),이동화(Dong Hua Li),심원보(Won Bo Sim),신형철(Hyungcheol Shin),이종덕(Jong Duk Lee),박병국(Byung-Gook Park) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
It is relatively hard to observe the program/erase operation efficiency in the flash memory device fabricated on the silicon-on-insulator (SOI), since sal MOSFET devices have the floating bodies. This property is quite different from that of bulk devices where the operation efficiency has relatively stronger dependence on the back substrate bias. In this work, the dependency of operation efficiency of sal memory device on implementation factors such as SOI thickness and channel concentration is investigated with the aid of the numerical device simulation.
신뢰성 있는 동작을 위한 수직 구조 플래시 메모리의 공정 및 전압 조건의 최적화 연구
조성재(Seongjae Cho),박일한(Il Han Park),이정훈(Jung Hoon Lee),윤장근(Jang-Gn Yun),김두현(Doo-Hyun Kim),이길성(Gil Sung Lee),김윤(Yun Kim),이동화(Dong Hua Li),신형철(Hyungcheol Shin),이종덕(Jong Duk Lee),박병국(Byung-Gook Park) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
Various efforts have been devoted to maximizing memory array densities nowadays. It cannot be overestimated that developments in both novel structures and process engineering should be accomplished to heighten the density. In this study, a novel structure in three-dimension is introduced Furthermore, we investigated the paired cell interference (PCI) which inevitably occurs in the read operation for this kind of 3-D memory devices Ways of establishing the read operation bias schemes for reliable operation are also examined.