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2-bit Recessed Channel SONOS Memory with Vertical Split Gate Structure
윤장근(Jang-Gn Yun),박일한(Il Han Park),조성재(Seongjae Cho),이정훈(Jung Hoon Lee),김두현(Doo-Hyun Kim),이길성(Gil Sung Lee),김윤(Yoon Kim),이동화(Dong-Hua Lee),박세환(Se-Hwan Park),심원보(Won-Bo Sim),이종덕(Jong-Duk Lee),박병국(Byung- 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
A 2-bit recessed channel SONOS memory with vertical split gate structure is characterized through 2-dimensional numerical simulation. With a long effective channel length, this device is immune to the short channel effect [1]. The charge storage nodes are self-lifted from the bottom-side of channel and hence the second-bit effect is effectively suppressed. Furthermore, increased charge injection efficiency is expected because of the split gate structure. Therefore, enhanced programming characteristics with low second-bit effect can be achieved with simpler fabrication processes compared with the fanner methods [2], [3].
수직형 4-비트 SONOS를 이용한 고집적화된 3차원 NOR 플래시 메모리
김윤,윤장근,조성재,박병국,Kim, Yoon,Yun, Jang-Gn,Cho, Seong-Jae,Park, Byung-Gook The Institute of Electronics and Information Engin 2010 電子工學會論文誌-CI (Computer and Information) Vol.47 No.2
수직형 채널을 가지는 4-비트 SONOS 플래시 메모리를 이용하여, 고집적화된 3차원 형태의 NOR 플래시 메모리 어레이를 제안하였다. 수직형 채널을 가지기 때문에, 집적도의 제한 없이 충분히 긴 채널을 가질 수 있다. 이로 인하여, 짧은 채널의 멀티 비트 메모리에서 발생할 수 있는 비트 간의 간섭효과, 짧은 채널 효과, 및 전하 재분포 현상을 해결 할 수 있다. 또한, 제시된 어레이는 3차원 형태를 기반으로 고집적화되어, 발표된 NOR 중에서 최소의 셀 크기 값인 $1.5F^2$/bit을 가진다. We proposed a highly integrated 3-dimensional NOR Flash memory array by using vertical 4-bit SONOS NOR flash memory. This structure has a vertical channel, so it is possible to have a long enough channel without extra cell area. Therefore, we can avoid second-bit effect, short channel effect, and redistribution of injected charges. And the proposed array structure is based on three-dimensional integration. Thus, we can obtain a NOR flash memory having $1.5F^2$/bit cell size.
Nano-scale CMOS를 위한 Ni-germano Silicide의 열 안정성 연구
황빈봉,오순영,윤장근,김용진,지희환,김용구,왕진석,이희덕,Huang, Bin-Feng,Oh, Soon-Young,Yun, Jang-Gn,Kim, Yong-Jin,Ji, Hee-Hwan,Kim, Yong-Goo,Wang, Jin-Suk,Lee, Hi-Deok 한국전기전자재료학회 2004 전기전자재료학회논문지 Vol.17 No.11
In this paper, novel methods for improvement of thermal stability of Ni-germano Silicide were proposed for nano CMOS applications. It was shown that there happened agglomeration and abnormal oxidation in case of Ni-germano Silicide using Ni only structure. Therefore, 4 kinds of tri-layer structure, such as, Ti/Ni/TiN, Ni/Ti/TiN, Co/Ni/TiN and Ni/Co/TiN were proposed utilizing Co and Ti interlayer to improve thermal stability of Ni-germano Silicide. Ti/Ni/TiN structure showed the best improvement of thermal stability and suppression of abnormal oxidation although all kinds of structures showed improvement of sheet resistance. That is, Ti/Ni/TiN structure showed only 11 ohm/sq. in spite of 600 $^{\circ}C$, 30 min post silicidation annealing while Ni-only structure show 42 ohm/sq. Therefore, Ti/Ni/TiN structure is highly promising for nano-scale CMOS technology.
3차원으로 적층된 수직형 NAND 플래시 메모리 특성 분석
김윤(Yoon Kim),윤장근(Jang-Gn Yun),박세환(Se Hwan Park),김완동(Wandong Kim),박병국(Byung-Gook Park) 대한전자공학회 2010 대한전자공학회 학술대회 Vol.2010 No.6
The characteristic of vertical NAND flash memory cell array is investigated by numerical simulation. The gap size between word lines should be reduced for bit line current drivability. Also, channel hole size is the critical parameter that determine program speed. These results will be the important issues of the 3D stacked vertical NAND array for reliable memory operation.
수직형 4-비트 SONOS를 이용한 고집적화된 3차원 NOR 플래시 메모리
김윤(Yoon Kim),윤장근(Jang-Gn Yun),조성재(Seongjae Cho),박병국(Byung-Gook Park) 대한전자공학회 2010 電子工學會論文誌-SD (Semiconductor and devices) Vol.47 No.2
수직형 채널을 가지는 4-비트 SONOS 플래시 메모리를 이용하여, 고집적화된 3차원 형태의 NOR 플래시 메모리 어레이를 제안하였다. 수직형 채널을 가지기 때문에, 집적도의 제한 없이 충분히 긴 채널을 가질 수 있다. 이로 인하여, 짧은 채널의 멀티 비트 메모리에서 발생할 수 있는 비트 간의 간섭효과, 짧은 채널 효과, 및 전하 재분포 현상을 해결 할 수 있다. 또한, 제시된 어레이는 3차원 형태를 기반으로 고집적화되어, 발표된 NOR 중에서 최소의 셀 크기 값인 1.5F²/bit을 가진다. We proposed a highly integrated 3-dimensional NOR Flash memory array by using vertical 4-bit SONOS NOR flash memory. This structure has a vertical channel, so it is possible to have a long enough channel without extra cell area. Therefore, we can avoid second-bit effect, short channel effect, and redistribution of injected charges. And the proposed array structure is based on three-dimensional integration. Thus, we can obtain a NOR flash memory having 1.5F²/bit cell size.
수직 채널을 갖는 4-비트 SONOS 노어 플래시 메모리
김윤(Yoon Kim),윤장근(Jang-Gn Yun),박일한(Il Han Park),조성재(Seong Jae Cho),이정훈,이길성,김두현,이동화,심원보,신형철(Hyungcheol Shin),이종덕(Jong Duk Lee),박병국(Byung-Gook Park) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
We proposed a vertical 4-bit SONOS NOR flash memory. This structure has the vertical channel, so it can be possible to have a long channel without extra cell area. Also, we can avoid second-bit effect and short channel effect. And the proposed array structure is based on three-dimensional integration. Thus, we can obtain NOR flash memory having 1.5F²/bit cell size.
SOI 기판 상에 구현된 플래시 메모리의 구현 조건에 대한 프로그램 동작 효율의 의존성
조성재(Seongjae Cho),박일한(Il Han Park),이정훈(Jung Hoon Lee),윤장근(Jang-Gn Yun),김두현(Doo-Hyun Kim),이길성(Gil Sung Lee),이동화(Dong Hua Li),심원보(Won Bo Sim),신형철(Hyungcheol Shin),이종덕(Jong Duk Lee),박병국(Byung-Gook Park) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
It is relatively hard to observe the program/erase operation efficiency in the flash memory device fabricated on the silicon-on-insulator (SOI), since sal MOSFET devices have the floating bodies. This property is quite different from that of bulk devices where the operation efficiency has relatively stronger dependence on the back substrate bias. In this work, the dependency of operation efficiency of sal memory device on implementation factors such as SOI thickness and channel concentration is investigated with the aid of the numerical device simulation.
2-bit/cell Folded Split Gate Flash Memory의 제작 방법
박세환(Se Hwan Park),박일한(Il Han Park),조성재(SeongJae Cho),윤장근(Jang-Gn Yun),이정훈(Jung Hoon Lee),이동화(Dong Hua Li),김두현(Doo-Hyun Kim),이길성(Gil Sung Lee),김윤(Yoon Kim),이종덕(Jong Duk Lee),박병국(Byung-Gook Park) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
A new 2-bit/cell SONOS flash memory device is designed. The device has recessed channel and a supplementary gate named as a select gate. The designed structure looks like a folded form of conventional one, so we call the device Folded Split Gate (FSG) flash memory
신뢰성 있는 동작을 위한 수직 구조 플래시 메모리의 공정 및 전압 조건의 최적화 연구
조성재(Seongjae Cho),박일한(Il Han Park),이정훈(Jung Hoon Lee),윤장근(Jang-Gn Yun),김두현(Doo-Hyun Kim),이길성(Gil Sung Lee),김윤(Yun Kim),이동화(Dong Hua Li),신형철(Hyungcheol Shin),이종덕(Jong Duk Lee),박병국(Byung-Gook Park) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
Various efforts have been devoted to maximizing memory array densities nowadays. It cannot be overestimated that developments in both novel structures and process engineering should be accomplished to heighten the density. In this study, a novel structure in three-dimension is introduced Furthermore, we investigated the paired cell interference (PCI) which inevitably occurs in the read operation for this kind of 3-D memory devices Ways of establishing the read operation bias schemes for reliable operation are also examined.