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ULSI급 CMOS 소자 특성 분석을 위한 몬테 카를로 이온 주입 공정 시뮬레이션시의 효율적인 가상 이온 발생법
손명식,이진구,Son, Myeong-Sik,Lee, Jin-Gu 대한전자공학회 2001 電子工學會論文誌-SD (Semiconductor and devices) Vol.38 No.11
ULSI급 CMOS 소자를 개발, 제작하고 또한 그것의 전기적 특성을 정확히 분석하기 위해서는 공정 및 소자 시뮬레이터의 사용이 필수적이다. 대면적 몬테 카를로 시뮬레이션 결과가 다차원 소자 시뮬레이터의 입력으로 사용되려면 과도한 입자수의 증가로 비효율성을 띄게 된다. 본 논문에서는 이러한 문제를 해결하기 위해 3차원 몬테 카를로 이온 주입 시뮬레이터인 TRICSI 코드를 이용하여 물리적으로 타당하며 또한 효율적으로 시뮬레이션 입자 수를 증가시켜 대면적 이온 주입시의 3차원 통계 분포의 잡음 영역을 최소화하는 방법을 제안하였다. 후속 공정인 열확산 공정이나 RTA(급속 열처리) 공정의 확산 방정식을 푸는 경우 발산을 막기 위해 몬테 카를로 시뮬레이션 결과의 통계 분포에 대한 후처리 과정으로 3차원 셀을 이용한 보간 알고리듬을 적용하였다. 시뮬레이션 수행 결과 가상 궤적 발생법(split-trajectory method)만을 사용한 것에 비해 계산 시간은 2배로 늘이지 않는 범위에서 10배 이상의 이온 입자 생성 분포를 얻을 수 있다. It is indispensable to use the process and device simulation tool in order to analyze accurately the electrical characteristics of ULSI CMOS devices, in addition to developing and manufacturing those devices. The 3D Monte Carlo (MC) simulation result is not efficient for large-area application because of the lack of simulation particles. In this paper is reported a new efficient simulation strategy for 3D MC ion implantation into large-area application using the 3D MC code of TRICSI(TRansport Ions into Crystal Silicon). The strategy is related to our newly proposed split-trajectory method and ion-splitting method(ion-shadowing approach) for 3D large-area application in order to increase the simulation ions, not to sacrifice the simulation accuracy for defects and implanted ions. In addition to our proposed methods, we have developed the cell based 3D interpolation algorithm to feed the 3D MC simulation result into the device simulator and not to diverge the solution of continuous diffusion equations for diffusion and RTA(rapid thermal annealing) after ion implantation. We found that our proposed simulation strategy is very computationally efficient. The increased number of simulation ions is about more than 10 times and the increase of simulation time is not twice compared to the split-trajectory method only.
비정질 및 다결정 실리콘 TFT-LCD에서의 플리커(flicker) 현상 비교 분석 연구
손명식,송민수,유건호,장진,Son, Myung-Sik,Song, Min-Soo,Yoo, Keon-Ho,Jang, Jin 대한전자공학회 2003 電子工學會論文誌-SD (Semiconductor and devices) Vol.40 No.1
In this paper, we present results of the comparative analysis of the flicker phenomena in the poly-Si TFT-LCD and a-Si:H TFT-LCD arrays for the development and manufacturing of wide-area and high-quality TFT-LCD displays. We used four different types of TFTs; a-Si:H TFT, excimer laser annealed (ELA) poly-Si TFT, silicide mediated crystallization (SMC) poly-Si TFT, and counter-doped lateral body terminal (LBT), poly-Si TFT. We defined the electrical quantity of the flicker so that we could compare the flickers quantitatively for four different 40" UXGA TFT-LCDs. We identify three factors contributing to the flicker, such as charging time, kickback voltage and leakage current, and analyze how much each of three factors give rise to the flincker in the different TFT-LCD arrays. In addition, we suggest and show that, in the case of the poly-Si TFT-LCD arrays, the low-level (minimum) gate voltages should be carefully chosen to minimize the flicker because of their larger leakage currents compared with a-Si TFT-LCD arrays.
손명식,Son, Myung-Sik 한국진공학회 2013 Applied Science and Convergence Technology Vol.22 No.6
본 논문은 InP 식각정지층을 갖는 MHEMT 소자의 항복전압을 증가시키기 위한 시뮬레이션 설계 논문이다. MHEMT 소자의 게이트 리세스 구조 및 채널 구조를 변경하여 시뮬레이션을 수행하였고 비교 분석하였다. MHEMT 소자의 드레인 측만을 완전히 제거한 비대칭 게이트 리세스 구조인 경우 $I_{dss}$ 전류가 90 mA에서 60 mA로 줄어들지만 항복 전압은 2 V에서 4 V로 증가함을 확인하였다. 이는 $Si_3N_4$ 보호층과 InAlAs 장벽층 사이의 계면에서 형성되는 전자-포획 음의 고정전하로 인해 채널층에서의 전자 공핍이 심화되어 나타나는 현상으로 이는 채널층의 전류를 감소시켜 충돌이온화를 적게 형성시켜 항복전압을 증가시킨다. 또한, 동일한 구조의 비대칭 게이트 리세스 구조에서 채널층을 InGaAs/InP 복합 채널로 바꾸어 설계한 구조에서는 항복전압이 5 V로 증가하였다. 이는 높은 드레인 전압에서 InP 층의 적은 충돌이온화와 이동도로 인해 전류가 더 감소했기 때문이다. This paper is for the simulation design to enhance the breakdown voltage of MHEMTs with an InP-etchstop layer. Gate-recess and channel structures has been simulated and analyzed for the breakdown of the MHEMT devices. The fully removed recess structure at the drain side of MHEMT shows that the breakdown voltage enhances from 2 V to almost 4 V as the saturation current at gate voltage of 0 V is reduced from 90 mA to 60 mA at drain voltage of 2 V. This is because the electron-captured negatively fixed charges at the drain-side interface between the InAlAs barrier and the $Si_3N_4$ passivation layers deplete the InGaAs channel layer more and thus decreases the electron current passing the channel layer and thus the impact ionization in the channel become smaller. In addition, the replaced InGaAs/InP composite channel with the same thickness in the same asymmetrically recessed structure increases the breakdown voltage to 5 V due to the smaller impact ionization and mobility of the InP layer at high drain voltage.
GaAs 기반 In_(0.52)Al_(0.48)As/In_(0.53)Ga_(0.47)As 이종접합 구조를 갖는 MHEMT 소자의 DC 특성에 대한 calibration 연구
손명식 한국반도체디스플레이기술학회 2011 반도체디스플레이기술학회지 Vol.10 No.1
Metamorphic HEMTs (MHEMTs) have emerged as excellent challenges for the design and fabrication of high-speed HEMTs for millimeter-wave applications. Some of improvements result from improved mobility and larger conduction band discontinuity in the channel, leading to more efficient modulation doping, better confinement, and better device performance compared with conventional pseudomorphic HEMTs (PHEMTs). For the optimized device design and development, we have performed the calibration on the DC characteristics of our fabricated 0.1㎛ Γ-gate MHEMT device having the modulation-doped In_(0.52)Al_(0.48)As/In_(0.53)Ga_(0.47)As heterostructure on the GaAs wafer using the hydrodynamic transport model of a commercial 2D ISE-DESSIS device simulator. The well-calibrated device simulation shows very good agreement with the DC characteristic of the 0.1㎛ Γ-gate MHEMT device. We expect that our 파라미터 보정 result can help design over-100-GHz MHEMT devices for better device performance.
InP 식각정지층을 갖는 MHEMT 소자의 InGaAs/InP 복합 채널 항복 특성 시뮬레이션
손명식 한국반도체디스플레이기술학회 2013 반도체디스플레이기술학회지 Vol.12 No.4
This paper is for enhancing the breakdown voltage of MHEMTs with an InP-etchstop layer. The fully removed recess structure in the drain side of MHEMT shows that the breakdown voltage enhances from 2V to 4V in the previous work. This is because the surface effect at the drain side decreases the channel current and the impact ionization in the channel at high drain voltage. In order to increase the breakdown voltage at the same asymmetric gate-recess structure, the InGaAs channel structure is replaced with the InGaAs/InP composite channel in the simulation. The simulation results with InGaAs/InP channel show that the breakdown voltage increases to 6V in the MHEMT as the current decreases. In this paper, the simulation results for the InGaAs/InP channel are shown and analyzed for the InGaAs/InP composite channel in the MHEMT.
손명식 한국반도체디스플레이기술학회 2021 반도체디스플레이기술학회지 Vol.20 No.4
In this paper, the measurements of received power was shown and compared in two developed 5.8GHz 25W wireless charging systems. One is the system using commercial transmission antenna, and the other is the system using transmission antenna combined with metamaterial. The system combined with metamaterial shows higher received power due to negative reflective index of metamaterial. In addition, a comparative analysis of the systems shows that the transmission efficiency in the systems can decrease the real gain of transmission antenna due to higher side robe of beam pattern. The side robe beams of transmitting antenna interferes transmitted beam with the reflected beams from the bottom region due to the side robes. The failure problems of the RF wireless charging systems are discussed and proposed in order to charge mobile devices through the RF wireless charging system.