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박종강,김명하,김종태 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.1
Single Event Transient has a critical impact on highly integrated logic circuits which are currently common in various commercial and consumer electronic devices. Reliability against the soft and intermittent faults will become a key metric to evaluate such complex system on chip designs. Our previous work analyzing soft errors was focused on parallelizing and optimizing error propagation procedures for individual transient faults on logic and sequential cells. In this paper, we present a new propagation technique where a fault binary decision diagram (BDD) continues to merge every new fault generated from the subsequent logic gate traversal. BDD-based transient fault analysis has been known to provide the most accurate results that consider both electrical and logical properties for the given design. However, it suffers from a limitation in storing and handling BDDs that can be increased in size and operations by the exponential order. On the other hand, the proposed method requires only a visit to each logic gate traversal and unnecessary BDDs can be removed or reduced. This results in an approximately 20-200 fold speed increase while the existing parallelized procedure is only 3-4 times faster than the baseline algorithm.
A VLSI Design for Digital Pre-distortion with Pipelined CORDIC Processors
박종강,문준영,김경훈,양영구,김종태 대한전자공학회 2014 Journal of semiconductor technology and science Vol.14 No.6
In a wireless communications system, a pre-distorter is often used to compensate for the nonlinear distortions that result from operating a power amplifier near the saturation region, thereby improving system performance and increasing the spectral efficiency for the communication channels. This paper presents a new VLSI design for the polynomial digital pre-distorter (DPD). The proposed DPD uses a Coordinate Rotation Digital Computing (CORDIC) processor and a PD process with a fully-pipelined architecture. Due to its simple and regular structure, it can be a competitive design when compared to existing polynomial-type and approximated DPDs. Implementing a fifth-order distorter with the proposed design requires only 43,000 logic gates in a 0.35 μm CMOS standard cell library.
Soft IP Compiler for a Reed-Solomon Decoder
박종강,김종태 한국전자통신연구원 2003 ETRI Journal Vol.25 No.5
In this paper, we present a soft IP compiler for the Reed-Solomon decoder that generates a fully synthesizableVHDL core exploiting characteristic parameters anddesign constraints that we newly classify for the soft IP. Itproduces a structural design with an estimable regulararchitecture based on a finite state machine with adatapath (FSMD). Since characteristic parametersprovide different design points on the design space, usingone of two simple procedures called the constructivesearch with area increment (CSAI) and constructivesearch with speed decrement (CSSD) for design spaceexploration, the core compiler makes it possible for an IPuser to create the Reed-Solomon decoder with appropriatesub-architectures without synthesizing many models. Experimental results show that the IP compiler can applyto several industry standards.
Analysis of Single-event Upset for SRAM Devices by Using the MC-50 Cyclotron
박종강,권순규,이승욱,김종태,채종서,신재원,홍승우 한국물리학회 2011 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.58 No.52
When high-energy particles hit electronic memory elements, stored data can be changed by the excessive charge produced by the collisions. This bit-flip error is known as single event upset (SEU). Even at sea-level, the occurrence of SEU in electronic devices is growing as the geometry of devices gets smaller and the supply voltage becomes lower. We extract the neutron SEU cross sections for commercial SRAM devices by using the MC-50 cyclotron accelerator at Korea Institute of Radiological & Medical Sciences (KIRAMS). To extract the SEU cross sections as a function of the neutron energy, we propose an approximate subtraction method to take into account the non-monoenergetic nature of the neutron beam from the MC-50 cyclotron. Our results for the SEU cross sections agree within a factor of 2 ∼ 3 with those of previous studies done in other facilities.
IP Compiler for a Soft Input Viterbi Decoder
박종강,JongTaeKim,KiBoKim 한국물리학회 2002 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.41 No.6
Since aspects of design-reuse depend on the application, it is important to design a reliable intellectual property (IP) model that satisfies several design constraints with a lower design cost and a shorter design time. This can be achieved by using early design-space exploration consisting of performance and area estimates of all applicable designs within the design constraints. We introduce a fully parameterized Viterbi IP compiler which generates a specific Viterbi decoder with a shorter design time. The design-space exploration in our IP compiler consisting of an area/time estimator and a parameter selector using the area/time ratio, can help the IP user to obtain an optimal IP model for a specified application area. The generated soft IPs of the Viterbi decoder are fully synthesizable with the Synopsys Design Compiler and the Examplar Logic's Leonardo Spectrum for Altera. Experimental results show that this IP compiler can produce competitive designs.
An Efficient Error Detection Technique for 3D Bit-Partitioned SRAM Devices
윤흥선,박종강,김종태 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.5
As the feature sizes and the operating charges continue to be scaled down, multi-bit soft errors are becoming more critical in SRAM designs of a few nanometers. In this paper, we propose an efficient error detection technique to reduce the size of parity bits by applying a 2D bit-interleaving technique to 3D bit-partitioned SRAM devices. Our proposed bit-interleaving technique uses only 1/K (where K is the number of dies) parity bits, compared with conventional bit-interleaving structures. Our simulation results show that 1/K parity bits are needed with only a 0.024-0.036% detection error increased over that of the existing bit-interleaving method. It is also possible for our technique to improve the burst error coverage, by adding more parity bits.
변용기,박종강,김종태,Byun, Yong-Ki,Park, Jong-Kang,Kim, Jong-Tae 한국조명전기설비학회 2006 조명·전기설비학회논문지 Vol.20 No.6
회로 전송선 배선 시 신호선은 직선의 형태와 방향을 바꾸기 위한 구부러지는 형태를 가진다. 차동 신호선의 정확한 등가회로는 이러한 전송선 구조의 시 공간 영역에서의 신호적 특성과 인접 신호선들 간의 영향을 평가할 수 있게 해준다. 이를 위해 기존의 몇 몇 CAD Tool들이 등가 회로 모델과 그 파라미터 값들을 추출 해주기도 하지만, 이는 큰 연산량과 시간을 요구한다. 본 논문에서는 구부러진 차동 신호선의 등가회로를 모델링하기 위해 기본적 모델인 RLC-모델의 파라미터 값을 유전 알고리듬을 이용하여 추출하는 방법을 제시한다. 본 방법에 의해 더욱 빠르게 물리적 구조를 갖는 차동 신호선의 등가회로를 모델링 할 수 있다. Routing signal lines in PCB, line shapes would be straight or bent. time-domain and frequency-domain evaluation of the signal property and interference are archived by precise Modeling of differential signal line. Some of CAD tools can extract equivalent circuit model parameters. but it takes a long time and heavy loads. This paper introduces a basic RLC equivalent circuit model parameter extraction technique for bent differential structures using genetic algorithm by this technique, we can model equivalent circuit of bent differential structures more faster.
An Efficient Overlapped LDPC Decoder with a Upper Dual-diagonal Structure
변용기,박종강,권순규,김종태 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.1
A low density parity check (LDPC) decoderprovides a most powerful error control capability formobile communication devices and storage systems,due to its performance being close to Shannon's limit. In this paper, we introduce an efficient overlappedLDPC decoding algorithm using a upper dualdiagonalparity check matrix structure. By means ofthis algorithm, the LDPC decoder can concurrentlyexecute parts of the check node update and variablenode update in the sum-product algorithm. In thisway, we can reduce the number of clock cycles periteration as well as reduce the total latency. Theproposed decoding structure offers a very simplecontrol and is very flexible in terms of the variable bitlength and variable code rate. The experiment resultsshow that the proposed decoder can complete thedecoding of codewords within 70% of the number ofclock cycles required for a conventional nonoverlappeddecoder. The proposed design also reducesthe power consumption by 33% when compared tothe non-overlapped design.