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새로운 구조의 구조의 ESD 보호소자를 내장한 고속-저 전압 LVDS 드라이버 설계에 관한 연구
김귀동,권중기,이재현,구용서 한국전기전자학회 2006 전기전자학회논문지 Vol.10 No.2
In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low signal swing range, maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps.And Zener Triggered SCR devices to protect the ESD phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V.Finally, The high speed I/O interface circuit with the low triggered ESD protection device in one-chip was designed.
김귀동,한태현,구용서,구진근,강상원,Kim, Gwi-Dong,Han, Tae-Hyeon,Gu, Yong-Seo,Gu, Jin-Geun,Gang, Sang-Won 한국전자통신연구원 1992 전자통신 Vol.14 No.3
이중 매몰층, $1.5\mum$ 에피두께, 이중 well, LOCOS 소자격리, LDD MOS 소자와 이중 다결정실리콘 전극을 갖는 바이폴라 소자에 의하여 구성된 BiCMOS 소자를 제작하였다. 제작된 소자를 측정 및 분석한 결과, 31단 CML 바이폴라($A_E=2X8\mum^2$)링 발진기와 31단 CMOS( $A_E=1.25X5\mum^2$) 인버터 링 발진기로부터 94ps/5V 와 330ps/12V의 게이트 전달 지연시간/소자 강복전압을 갖는 바이폴라 및 MOS소자특성을 얻을 수 있었다. 또한 BiCMOS 소자의 경우, 31단 BiCMOS 링 발진기로부터 약 700ps의 게이트 전달 지연시간을 얻었으며, 출력부하의 증가에 따른 속도의 감속비가 완만한 전기적 특성을 얻을 수 있었다.
새로운 구조의 ESD 보호소자를 내장한 고속-저 전압 LVDS 드라이버 설계에 관한 연구
김귀동,권종기,이재현,구용서,Kim, Kui-Dong,Kwon, Jong-Ki,Lee, KJae-Hyun,Koo, Yong-Seo 한국전기전자학회 2006 전기전자학회논문지 Vol.10 No.2
In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low signal swing range, maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD Phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, The high speed I/O interface circuit with the low triggered ESD protection device in one-chip was designed.
새로운 구조의 나노급 ESD 보호소자 설계 및 제작에 관한 연구
김귀동(Kim, Kui-Dong),이조운(Lee, Jo-Woon),박상조(Park, Sang-Jo),이윤식(Lee, Yoon-Sik),구용서(Koo, Yong-Seo) 한국전기전자학회 2005 전기전자학회논문지 Vol.9 No.2
본 연구에서는 보다 낮은 트리거 전압을 갖는 새로운 구조의 LVTSCR과 Triple-well SCR ESD 보호회로를 제안 및 설계하여 나노급 회로에 적용하고자 하였다. 제안된 LVTSCR은 약 9V, 약 7mA의 트리거 전압과 전류 및 약 7mA의 홀딩전압 특성을 가지며, 0.8KV(150mA/um) 정도의 ESD 감내 특성을 나타낸다. 한편 Triple-well SCR은 6V, 40mA의 트리거 전압을 가지며, substrate 및 gate 바이어스에 의해 트리거 전압이 4-5.5V 까지 감소하였다. This paper presents the new structural Low voltage LVTSCR and TWSCR ESD protection circuit. The proposed ESD protection circuit has lower triggering voltage than conventional circuits. And the LVTSCR has the triggering voltage of 9V, current of 7mA and can pass below 0.8KV (150mA/um). The triggering voltage of the Triple-well SCR measured to 6V and the current is 40mA. By the substrate and gate bias, the triggering voltage is lowered down to 4~5.5V.
김귀동(Kim Kwi-Dong),창상훈(Chang Sang-Hoon),한문섭(Han Moon-Sub),김왕곤(Kim Wang-Gon) 한국철도학회 2002 한국철도학회 학술발표대회논문집 Vol.- No.-
The harmonics in railway high voltage system is due to common use of 3 phase incoming bus and doing the power converter for traction system on the electric car(or electric locomotive). This paper, we analyze the harmonics mechanism and characteristics of railway high voltage system, also we analyze the problem according to the actual measurement about influence of harmonics on the railway high voltage system. And we proved the countermeasure device(passive filter or L-C filter) of harmonics applies in the field. The test result, we have know that the filter is not fit. Consequently, The countermeasure of harmonics for the railway high voltage system be able to resolve by another filter.