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구진근,김창일,박형호,권광호,현영철,서경수,남기수 한국전기전자재료학회 1996 電氣電子材料學會誌 Vol.9 No.3
The surface properties of AI(Si, Cu) alloy film after plasma etching using the chemistries of chlorinated and fluorinated gases with varying the etching time have been investigated using X-ray Photoelectron Spectroscopy. Impurities of C, Cl, F and O etc are observed on the etched AI(Si, Cu) films. After 95% etching, aluminum and silicon show metallic states and oxidized (partially chlorinated) states, copper shows Cu metallic states and Cu-Cl$_{x}$(x<l) bonds. The core level Cu 2p peak show broadening of the peaks with increasing the etching time from a pure Cu state and shake-up satellite structure with only 110% etched sample. From these results and the changes of Cu LMM auger peaks, it is found that Cu forms CuCl$_{x}$ (x<l) chlorinated compound after 90% and 95% etching, and CuCl$_{x}$ (1<x<2) after 110% etching. At the same time, aluminum shows Al-Cl and Al-F bonds while silicon show only Si-O bonds after 110% etching.ching.
다결정 실리콘 Self-align에 의한 바이폴라 트랜지스터의 제작
채상훈,구진근,김재련,이진효,Chae, Sang-Hun,Gu, Jin-Geun,Kim, Jae-Ryeon,Lee, Jin-Hyo 한국전자통신연구원 1985 전자통신 Vol.7 No.4
바이폴라 소자로 구성된 회로가 양호한 특성을 갖기 위해서는 개별 소자의 동작 속도, 집적도 및 전력 소비 특성이 좋아야 한다. 그런데 지금까지 주로 사용해온 기존의 SBC 바이폴라 트랜지스터로는 이들 특성을 개선하는 데는 한계가 있었다. 일반적으로 바이폴라 트랜지스터는 면적이 줄어듦에 따라 이들 특성이 개선되므로 본 연구에서는 SBC 방법과는 다른 PSA 공정 방법을 개발하였다. 즉, 소자 격리에서의 종래의 PN 접합에 의한 방법과 다른 산화막에 의한 방법을 도입하였고 또한 에미터, 베이스 사이의 거리를 최소로 줄이기 위하여 다결정 실리콘에 의한 polysilicon self-align 방법으로 에미터 및 베이스를 형성시켰다. A polysilicon self-aligned bipolar n-p-n transistor structure is described, which can be used in high speed and high packing density LSI circuits The emitter of this transistor is separated less than $0.4\mum$ with base contact by polysilicon self-align technology. Through all the process, the active region of this device is not damaged. therefore a high performance device is obtained. Using the transistor with $3.0\mum$ design rules, a CML ring oscillator has per-gate minimum propagation delay time of 400 ps at 2.7 mW power consumption condition.
고 전력 DMOSFET 응용을 위한 트렌치 게이트 형성에 관한 연구
박훈수,구진근,이영기 한국전기전자재료학회 2004 전기전자재료학회논문지 Vol.17 No.7
In this study, the etched trench properties including cross-sectional profile, surface roughness, and crystalline defects were investigated depending on the various silicon etching and additive gases, For the case of HBr$He-O_2SiF_4$ trench etching gas mixtures, the excellent trench profile and minimum defects in the silicon trench were achieved. Due to the residual oxide film grown by the additive oxygen gas, which acts as a protective layer during trench etching, the undercut and defects generation in the trench were suppressed. To improve the electrical characteristics of trench gate, the hydrogen annealing process after trench etching was also adopted. Through the hydrogen annealing, the trench corners might be rounded by the silicon atomic migration at the trench corners having high potential. The rounded trench corner can afford to reduce the gate electric field and grow a uniform gate oxide. As a result, dielectric strength and TDDB characteristics of the hydrogen annealed trench gate oxide were remarkably increased compared to the non-hydrogen annealed one.
김상기,박일용,구진근,김종대 한국전기전자재료학회 2002 전기전자재료학회논문지 Vol.15 No.10
Linearly graded profiles on the field area oxide are frequently used in power integrated circuits to reduce the surface electric field when power devices are operated in forward or reverse blocking modes. It is shown here that tapered windows can be made using the difference of etch rates between the bottom and the top layer of TEOS film. Annealed TEOS films are etched at a lower rate than the TEOS film without annealing Process. The fast etching layer results in window walls having slopes in the range of 25$^{\circ}$∼ 80$^{\circ}$ with respect to the wafer surface. Taper etching technique by annealing the TEOS film applies to high voltage LDMOS, which is compatible with CMOS process, due to the minimum changes in both of design rules and thermal budget.