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공대영 ( Dae Young Kong ),은덕수 ( Duk Soo Eun ),배영호 ( Young Ho Bae ),이종현 ( Jong Hyun Lee ) 한국센서학회 2005 센서학회지 Vol.14 No.3
N/A The SOI structure with buried alumina was fabricated by ALD followed by bonding and etchback process. The interface of alumina and silicon was analyzed by CV measurements and cross section was investigated by SEM analysis. The density of interface state of alumina and silicon was 2.5E11/cm²-eV after high temperature annealing for wafer bonding. It was confirmed that the surface silicon layer was completely isolated from substrate by cross section SEM and AES depth profile. The device on this alumina SOI structure would have better thermal properties than that on conventional SOI due to higher thermal conductivity of alumina than that of silicon dioxide.
연요철(Anti-Glare) 구조의 표면 유리 기판을 가지는 고효율 태양전지 모듈
공대영,김동현,윤성호,배영호,류인식,조찬섭,이종현,Kong, Dae-Young,Kim, Dong-Hyun,Yun, Sung-Ho,Bae, Young-Ho,Yu, In-Sik,Cho, Chan-Seob,Lee, Jong-Hyun 한국진공학회 2011 Applied Science and Convergence Technology Vol.20 No.3
태양전지 모듈은 back sheet, 후면 충진재, 태양전지 cell, 전면 충진재, 전면 보호유리의 구성으로 되어 있다. Back sheet는 유리 또는 금속을 사용하는데 사용 재료에 따라 각각 유리봉입방식, 슈퍼스트레이트방식으로 구분된다. 태양전지를 보호하기 위한 충진재는 빛의 투과율 저하가 적은 poly vinyl butylo나 내습성이 뛰어난 ethylene vinyl acetate 등이 주로 이용된다. 유리봉입방식과 슈퍼스트레이트 방식의 공통점은 모듈 전면에 투과율과 내 충격 강도가 좋은 강화 유리를 사용하는 것이다. 하지만 현재 모듈의 전면 유리는 평탄한 표면 때문에 태양고도가 낮을 때 상대적으로 반사율이 높은 단점을 가지고 있다. 이러한 문제점을 해결하기 위한 방안으로 표면 유리에 요철(anti-glare) 구조를 형성하면 평면(bare) 구조의 표면에서 반사되는 태양광이 일부 태양전지 내부로 재입사가 일어나게 되어 표면 반사율이 낮아지게 되고, 이로 인하여 태양전지의 효율이 증가하게 된다. 특히 이러한 효과는 태양고도가 낮아졌을 때 요철(anti-glare) 구조에 의한 반사율의 감소가 증가하기 때문에 평면 구조보다 요철(anti-glare) 구조의 태양전지 모듈의 효율이 향상될 것이다. 본 논문에서는 요철(anti-glare) 구조의 유리와 평면 구조의 유리에서 태양고도의 고도 변화에 따른 반사와 투과 특성을 확인하기 위하여 입사광의 각도에 대한 반사율과 투과율을 측정하여 비교 분석하였다. 그리고 태양전지 cell 위에 요철(anti-glare) 구조의 유리와 평명 구조의 유리를 각각 위치 시킨 후 태양전지 cell의 효율 변화를 확인하였다. 태양전지 cell의 표면 구조에 따라 요철 구조의 유리 기판의 특성을 비교하기 위하여 태양전지 cell의 표면을 이방성 식각 용액을 이용하여 역피라미드 구조의 텍스쳐링 태양전지 cell과 평면 구조의 태양전지 cell을 각각 사용하여 비교하였다. Currently, solar module is using the two methods such as a glass-filled method or a super-straight method. The common point of these methods is to use glass structure on the front of solar module. However, the reflectance of the solar module is high depending on the height of the incident sunlight due to the flat surface of the module front glass. Purposed to solve these problems, AG (anti-glare) structures were formed on the glass surface. Next is fabrication methods of AG structure. First, uneven structure made by micro blaster equipment was dipped in Hydro-fluidic acid (HF) acid. HF acid process was carried out to remove particles and to make high transmittance. The reflectance and transmittance of the anti-glare glass was compared to those of the bare glass. The reflectance of anti-glare glass decreased approximately 1% compared with bare glass. The transmittance of anti-glare glass was similar to bare glass. According to the sample angle, the difference of the reflectance between bare glass and the anti-glare glass was about 19%. Isc and efficiency value of anti-glare glass on bare solar cell appeared about 3.01 mA and 0.228% difference compared with bare glass. Anti-glare glass on textured solar cell appeared about 9.46 mA and 0.741% difference compared with bare glass. As a result, the role of anti-glare in the substrate is to reduces the loss of sunlight reflected from the surface. In this study, therefore, AG structure on the solar cell was used to improve the efficiency of solar cell.
병렬 플라즈마 소스를 이용한 마이크로 LED 소자 제작용 GaN 식각 공정 시스템 개발
손보성,공대영,이영웅,김희진,박시현,Son, Boseong,Kong, Dae-Young,Lee, Young-Woong,Kim, Huijin,Park, Si-Hyun 한국반도체디스플레이기술학회 2021 반도체디스플레이기술학회지 Vol.20 No.3
We developed an inductively coupled plasma (ICP) etcher for GaN etching using a parallel plasma electrode source with a multifunctional chuck matched to it in order for the low power consumption and low process cost in comparison with the conventional ICP system with a helical-type plasma electrode source. The optimization process condition using it for the micro light-emitting diode (µ-LED) chip fabrication was established, which is an ICP RF power of 300 W, a chuck power of 200 W, a BCl<sub>3</sub>/Cl<sub>2</sub> gas ratio of 3:2. Under this condition, the mesa structure with the etch depth over 1 ㎛ and the etch angle over 75° and also with no etching residue was obtained for the µ-LED chip. The developed ICP showed the improved values on the process pressure, the etch selectivity, the etch depth uniformity, the etch angle profile and the substrate temperature uniformity in comparison with the commercial ICP. The µ-LED chip fabricated using the developed ICP showed the similar or improved characteristics in the L-I-V measurements compared with the one fabricated using the conventional ICP method
RIE 공정 조건에 의한 피라미드 구조의 블랙 실리콘 형성
조준환 ( Jun Hwan Jo ),공대영 ( Dae Young Kong ),조찬섭 ( Chan Seob Cho ),김봉환 ( Bong Hwan Kim ),배영호 ( Young Ho Bae ),이종현 ( Jong Hyun Lee ) 한국센서학회 2011 센서학회지 Vol.20 No.3
In this study, pyramid structured black silicon process was developed in order to overcome disadvantages of using wet etching to texture the surface of single crystalline silicon and using grass/needle-like black silicon structure. In order to form the pyramidal black silicon structure on the silicon surface, the RIE system was modified to equip with metal-mesh on the top of head shower. The process conditions were: SF6/O2 gas flow 15/15 sccm, RF power of 200 W, pressure at 50 mTorr~200 mTorr, and temperature at 5℃. The pressure did not affect the pyramid structure significantly. Increasing processing time increased the size of the pyramid, however, the size remained constant at 1 μm~2 μm between 15 minutes~20 minutes of processing. Pyramid structure of 1 μm in size showed to have the lowest reflectivity of 7 %~10 %. Also, the pyramid structure black silicon is more appropriate than the grass/needle-like black silicon when creating solar cells.
홍표환 ( Pyo Hwan Hong ),공대영 ( Dae Young Kong ),남재우 ( Jae Woo Nam ),이종현 ( Jong Hyun Lee ),조찬섭 ( Chan Seob Cho ),김봉환 ( Bong Hwan Kim ) 한국센서학회 2013 센서학회지 Vol.22 No.2
This study proposed a noble process to fabricate TSV (Through Silicon Via) structure which has lower cost, shorter production time, and more simple fabrication process than plating method. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process. The via hole was 100 ㎛ in diameter and 400 ㎛ in depth. A dielectric layer of SiO2 was formed by thermal oxidation on the front side wafer and via hole side wall. An adhesion layer of Ti and a seed layer of Au were deposited. Soldering process was applied to fill the via holes with solder paste and metal powder. When the solder paste was used as via hole metal line, sintering state and electrical properties were excellent. However, electrical connection was poor due to occurrence of many voids. In the case of metal powder, voids were reduced but sintering state and electrical properties were bad. We tried the via hole filling process by using mixing solder paste and metal powder. As a consequence, it was confirmed that mixing rate of solder paste (4) : metal powder (3) was excellent electrical characteristics.
a-SiOx Buffer Layer 삽입을 통한 고효율 비정질 실리콘 박막태양전지에 관한 및 연구
박승만(Park, Seung-Man),이선화(Lee, Sun-Hwa),공대영(Kong, Dae-Young),이원백(Lee, Wan-Back),정우원(Jung, Wu-Wan),이준신(Yi, Jun-Sin) 한국신재생에너지학회 2009 한국신재생에너지학회 학술대회논문집 Vol.2009 No.11
TCO/p/i/n 구조의 비정질 실리콘 박막 태양전지의 제작에 있어서 TCO계면과 p층사이의 이종접합에서의 큰 밴드갭 차이는 p층으로부터의 정공 재결합을 통하여 효율 저하의 원인이 된다. 이러한 재결합은 넓은 밴드갭을 가진 물질을 완충층으로 삽입함으로써 개선되어 질 수 있다. 본 논문에서는 비정질 실리콘 보다 넓은 광학적 밴드갭을 가지는 a-SiOx 박막을 완충층으로 사용하여 TCO/P 계면에서의 재결합 감소에 대한 시뮬레이션을 수행하였다. a-SiOX 박막 내에 포함된 산소의 양에 따라 밴드갭을 조절하여 1.8eV~2.0eV 사이의 완충층을 삽입하여 박막태양전지의 개방전압, 단락전류, 효율 등에 끼치는 영향을 ASA 시뮬레이션을 통하여 알아보았다.