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금속 유도 일측면 선결정화에 의해 제작된 다채널 다결정 실리콘 박막 트랜지스터 소자 및 회로의 전기적 특성 평가
황욱중,강일석,임성규,김병일,양준모,안치원,홍순구,Hwang, Wook-Jung,Kang, Il-Suk,Lim, Sung-Kyu,Kim, Byeong-Il,Yang, Jun-Mo,Ahn, Chi-Won,Hong, Soon-Ku 한국재료학회 2008 한국재료학회지 Vol.18 No.9
Electrical properties of multi-channel metal-induced unilaterally precrystallized polycrystalline silicon thin-film transistor (MIUP poly-Si TFT) devices and circuits were investigated. Although their structure was integrated into small area, reducing annealing process time for fuller crystallization than that of conventional crystal filtered MIUP poly-Si TFTs, the multi-channel MIUP poly-Si TFTs showed the effect of crystal filtering. The multi-channel MIUP poly-Si TFTs showed a higher carrier mobility of more than 1.5 times that of the conventional MIUP poly-Si TFTs. Moreover, PMOS inverters consisting of the multi-channel MIUP poly-Si TFTs showed high dynamic performance compared with inverters consisting of the conventional MIUP poly-Si TFTs.
선결정화법을 이용한 금속 유도 일측면 결정화에 의해 제작된 다결정 실리콘 박막 트랜지스터 소자 및 회로의 전기적 특성 개선 효과
황욱중,강일석,김영수,양준모,안치원,홍순구,Hwang, Wook-Jung,Kang, Il-Suk,Kim, Young-Su,Yang, Jun-Mo,Ahn, Chi-Won,Hong, Soon-Ku 한국진공학회 2008 Applied Science and Convergence Technology Vol.17 No.5
적층 박막 내에서의 상변화는 주변 층에 영향을 준다. 결정화가 게이트 절연층에 주는 영향이 제거된 선결정화법(precrystallization)이 금속 유도 일측면 결정화(metal-induced unilateral crystallization)에 의해 제작된 다결정 실리콘 박막 트랜지스터 소자 및 회로의 전기적 특성에 미치는 영향에 대하여 연구하였다. 이 방법으로 만들어진 소자는 일반적인 후 결정화(postcrystallization) 소자에 비하여 높은 전류 구동력을 보였다. 여기에 본 연구는 DC bias에 의한 ring oscillator의 특성 변화를 연구하였다. 선결정화된 실리콘 박막을 이용하여 제작한 PMOS inverter는 후결정화된 실리콘 박막을 이용하여 제작한 inverter에 비하여 매우 동적(dynamic)이고도 안정적인 특성을 보였다. The phase transformation in a film influences its surrounding. Effects of the precrystallization method, which removes influences on gate oxide caused by lateral crystallization, in metal-induced unilaterally crystallized polycrystalline silicon thin-film transistor devices and circuits were studied. Device by the method was shown to have a higher current drive, compared with conventional postcrystallized device. Moreover, we studied DC bias-induced changes in the performance of ring oscillator. PMOS inverters fabricated using precrystallized silicon films have very high dynamic and stable performance, compared with inverters fabricated using postcrystallized silicon films.
이형규,김성진,강일석,이기성,김기남,고진원,Lee, Hyung Gyoo,Kim, Sung Jin,Kang, Il-Suk,Lee, Gi Sung,Kim, Ki Nam,Koh, Jin Won 한국전기전자재료학회 2016 전기전자재료학회논문지 Vol.29 No.3
Graphene has a monolayer crystal structure formed with C-atoms and has been used as a base layer of HETs (hot electron transistors). Graphene HETs have exhibited the operation at THz frequencies and higher current on/off ratio than that of Graphene FETs. In this article, we report on the preliminary results of current characteristics from the HETs which are fabricated utilizing highly doped Si collector, graphene base, and 5 nm thin $Al_2O_3$ tunnel layers between the base and Ti emitter. We have observed E-B forward currents are inherited to tunneling through $Al_2O_3$ layers, but have not noticed the Schottky barrier blocking effect on B-C forward current at the base/collector interface. At the common-emitter configuration, under a constant $V_{BE}$ between 0~1.2V, $I_C$ has increased linearly with $V_{CE}$ for $V_{CE}$ < $V_{BE}$ indicating the saturation region. As the $V_{CE}$ increases further, a plateau of $I_C$ vs. $V_{CE}$ has appeared slightly at $V_{CE}{\simeq}V_{BE}$, denoting forward-active region. With further increase of $V_{CE}$, $I_C$ has kept increasing probably due to tunneling through thin Schottky barrier between B/C. Thus the current on/off ration has exhibited to be 50. To improve hot electron effects, we propose the usage of low doped Si substrate, insertion of barrier layer between B/C, or substrates with low electron affinity.
양면 열박리 테이프 기반 임시 접합 공정을 이용한 대면적 웨이퍼 레벨 고출력 전자패키지
황용식 ( Yong-sik Hwang ),강일석 ( Il-suk Kang ),이가원 ( Ga-won Lee ) 한국센서학회 2022 센서학회지 Vol.31 No.1
High-power devices, such as LEDs and radars, inevitably generate a large amount of heat, which is the main cause of shortening lifespan, deterioration in performance, and failure of electronic devices. The embedded IC process can be a solution; however, when applied to large-area substrates (larger than 8 in), there is a limit owing to the difficulty in the process after wafer thinning. In this study, an 8- in wafer-level high-power electronic package based on the embedded IC process was implemented with temporary bonding and debonding technology using double-sided thermal release tape. Good heat-dissipation characteristics were demonstrated both theoretically and experimentally. These findings will advance the commercialization of high-power electronic packaging.