TiO2−x –TiO2 Memristor Applications for Programmable Analog VLSI Circuits at 45 nm CMOS Technology Node

S. V. Abhay,Sanjay Vidhyadharan 한국전기전자재료학회 2021 Transactions on Electrical and Electronic Material Vol.22 No.4

Memristor-CMOS (MCM) technology combines CMOS processing with nano-scale memristors enabling a significant reduction in the silicon area as compared to CMOS-only counterparts. Moreover, the non-volatile memory characteristics of the memristor offers opportunity for new and innovative MCM hybrid VLSI circuits that can outperform conventional CMOS designs. MCM based hybrid, homogeneous re-configurable architectures have already gained immense popularity among digital VLSI designers. This paper explores application of TiO2−x –TiO2 charge trap memristor for programmable analog VLSI applications. The threshold adaptive memristor SPICE model has been used to evaluate the performance of the memristor in electronic design automation tool in conjunction with 45 nm CMOS devices. A digitally controlled MCM analog buffer, MCM binary phase shift keying modulator and a variable gain MCM differential amplifier has been presented in this paper. The MCM analog buffer has 81% greater gain-bandwidth product than the corresponding CMOS-only buffer and has an attenuation of −32 dB when the control signal is low. A MCM differential amplifier is proposed whose gain can be varied in both directions by shifting the operating point of the memristor through control signals, proving the advantages of using MCM technology for automatic gain control and other programmable analog VLSI applications. A MCM BPSK modulator circuit is also proposed which occupies 37.2% lesser silicon area than the conventional CMOS-only BPSK modulators, thus illustrating the utility of memristor in analog switching circuits.

Design of Low Power Capacitive Sensing Circuit with a High Resolution in CMOS Technology

Jung, Seung-Min The Korea Institute of Information and Commucation 2011 Journal of information and communication convergen Vol.9 No.3

This paper describes the possibility of a low-power, high-resolution fingerprint sensor chip. A modified capacitive detection circuit of charge sharing scheme is proposed, which reduces the static power dissipation and increases the voltage difference between a ridge and valley more than conventional circuit. The detection circuit is designed and simulated in 3.3V, 0.35${\mu}$m standard CMOS process, 40MHz condition. The result shows about 27% power dissipation reduction and 90% improvement of difference between a ridge and valley sensing voltage. The proposed circuit is more stable and effective than a typical circuit.

A Robust Resistive Fingerprint Sensor

Jung, Seung-Min The Korea Institute of Information and Commucation 2009 Journal of information and communication convergen Vol.7 No.1

A novel sensing scheme using resistive characteristics of the finger is proposed. ESD problem is more harmful than a capacitive fingerprint sensor in a resistive fingerprint sensor, because the sensor plate is directly connected to the sensing cell. The proposed circuit is more robust than conventional circuit for ESD. The sensor plate and sensing cell are isolated by capacitor. The pixel level simple detection circuit is fully digital operation unlike that of the capacitive sensing cell. The sensor circuit blocks are designed and simulated in a standard CMOS $0.35{\mu}m$ process. The proposed circuit is more stable and effective than a typical circuit.

VLSI Implementation of Forward Error Control Technique for ATM Networks

G. Padmavathi,R. Amutha,S.K. Srivatsa 한국전자통신연구원 2005 ETRI Journal Vol.27 No.6

length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very-large-scale integration(VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a 5 × 5 matrix of data cells in a Virtex-EXCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented.

Full-Chip Power/Performance Benefits of Carbon Nanotube-Based Circuits

Song, Taigon,Lim, Sung Kyu The Korea Institute of Information and Commucation 2015 Journal of information and communication convergen Vol.13 No.3

As a potential alternative to the complementary metal-oxide semiconductor (CMOS) technology, many researchers are focusing on carbon-nanotube field-effect transistors (CNFETs) for future electronics. However, existing studies report the advantages of CNFETs over CMOS at the device level by using small-scale circuits, or over outdated CMOS technology. In this paper, we propose a methodology of analyzing CNFET-based circuits and study its impact at the full-chip scale. First, we design CNFET standard cells and use them to construct large-scale designs. Second, we perform parasitic extraction of CNFET devices and characterize their timing and power behaviors. Then, we perform a full-chip analysis and show the benefits of CNFET over CMOS in 45-nm and 20-nm designs. Our full-chip study shows that in the 45-nm design, CNFET circuits achieve a 5.91×/3.87× (delay/power) benefit over CMOS circuits at a density of 200 CNTs/µm. In the 20-nm design, CNFET achieves a 6.44×/3.01× (delay/power) benefit over CMOS at a density of 200 CNTs/µm.

저 전력 회로에 적합한 고 성능 이중 에지 트리거 플립플롭 설계

추광범,김정범 한국정보기술학회 2014 한국정보기술학회논문지 Vol. No.

Dual edge-triggered flip-flop is a sequential element which samples data at both positive as well as negative edges of the clock. The main advantage of using dual edge triggered flip-flop is that it allows one to maintain a constant throughput while operating at only half the clock frequency. This paper propose a high performance dual edge-triggered flip-flop for low power applications. Comparing to the previous work, the proposed circuit gives the reduction of the power dissipation by 18.1% and the improvement of the power-delay-product (PDP) by 16.1%. The proposed circuits are implemented by 0.18㎛ CMOS standard process with 1.8V supply voltage. The validity and effectiveness of the proposed circuits are verified through the HSPICE simulation. 이중 에지 트리거 플립플롭 (dual edge-triggered flip flop)은 클록의 하향에지 (negative edge) 뿐만 아니라 상향에지 (positive edge)에서 데이터를 샘플링 (sampling)하는 순차회로 요소이다. 이중 에지 트리거 플립플롭은 클록 주파수의 오직 반주기에서 동작하는 동안 변함없는 처리량 (throughput)이 유지한다는 장점을 갖는다. 본 논문에서는 저전력 회로에 적용이 가능한 이중 에지 트리거 플립플롭을 제안하고 특성을 비교하였으며, 1.8V의 공급전압과 0.18um CMOS 공정 기술을 사용하여 설계하였다. 제안한 회로는 기존 연구에 비해 18.1%의 전력소비를 절감하였으며, 16.1%의 전력소비와 지연시간의 곱 (power-delay-product, PDP) 특성을 개선하였다. 제안한 회로는 HSPICE 시뮬레이션을 통하여 타당성을 입증하였다.

A Nanopower Supply-Insensitive CMOS Vth Extractor

Jing Wang,Qiang Li,Li Ding,Yasuaki Inoue 대한전자공학회 2015 ITC-CSCC :International Technical Conference on Ci Vol.2015 No.6

In this paper, a nanopower supply-insensitive CMOS threshold voltage extractor circuit is proposed, which can meet today’s industry demands for portable devices to operate under very low power consumption and large supply voltage variations. Simulation results, based on CMOS 0.18um process, show that, the threshold voltage of CMOS transistors can be extracted with less than 0.01% error for wide power supply range. At the same time, the proposed Vth extractor can operated with less than 300nW power consumption for 1.3V power supply.

A Study on the VLSI Implementation of Fingerprint Thinning Processors Using Hybrid GDI Technique

Seungmin Jung 한국정보과학회 2023 Journal of Computing Science and Engineering Vol.17 No.1

$256{\times}256$ 픽셀 어레이 저항형 지문센서

정승민,Jung, Seung-Min 한국정보통신학회 2009 한국정보통신학회논문지 Vol.13 No.3

본 논문에서는 개선된 회로를 적용한 $256{\times}256$ 픽셀 저항형 지문센서를 제안하고 있다. 단위 픽셀 수준의 센싱회로는 가변적인 전류를 전압으로 변환하여 이진 디지털 신호로 만든다. 정전기에 효과적으로 대처할 수 있는 인접 픽셀 간 전기적 차폐 레이아웃 구조를 제안하고 있다. 전체회로는 단위 센서 회로를 확장하여 ASIC 설계방식을 통하여 설계한 뒤 로직 및 회로에 대하여 모의실험을 하였다. 전체회로는 $0.35{\mu}m$ 표준 CMOS 공정규칙을 적용하여 센서블록은 전주문 방식을 적용하고 전체 칩은 자동배선 툴을 이용하여 반주문 방식으로 레이아웃을 실시하였다. In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure around the unit pixel. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

A Two-bit Bus-Invert Coding Scheme With a Mid-level State Bus-Line for Low Power VLSI Design

Yoon, Myungchul The Institute of Electronics and Information Engin 2014 Journal of semiconductor technology and science Vol.14 No.4

A new bus-invert coding circuit, called Two-bit Bus-Invert Coding (TBIC) is presented. TBIC partitions a bus into a set of two-bit sub-buses, and applies the bus-invert (BI) algorithm to each sub-bus. Unlike ordinary BI circuits using invert-lines, TBIC does not use an invert-line, so that it sends coding information through a bus-line. To transmit 3-bit information with 2 bus-lines, TBIC allows one bus-line to have a mid-level state, called M-state. TBIC increases the performance of BI algorithm, by suppressing the generation of overhead transitions. TBIC reduces bus transitions by about 45.7%, which is 83% greater than the maximum achievable performance of ordinary BI with invert-lines.