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Junyoung Song,Inhwa Jung,Minyoung Song,Young-Ho Kwak,Sewook Hwang,Chulwoo Kim IEEE 2013 IEEE transactions on circuits and systems. a publi Vol.60 No.2
<P>This paper proposes a 2.7 Gb/s referenceless transceiver with weighted PFD for frequency detection of random signals. A single loop referenceless CDR is also proposed to overcome the disadvantages of a dual loop CDR. The ANSI 8b/10b encoder & decoder with the scrambler, the serializer & de-serializer, and the output driver with pre-emphasis are included in the proposed transceiver architecture for DisplayPort v1.1a. The jitter of the generated clock at the Tx PLL is 3.28 ps<SUB>rms</SUB> at 2.7 Gb/s with 1.2 V supply. The eye opening of the transmitter output with 3 m cable is 0.54 UI. The measured jitter of the recovered clock at the CDR is 1.57 ps<SUB>rms</SUB>, and BER is less than 10<SUP>-12</SUP>. The receiver consumes 23 mW at 2.7 Gb/s with 1.2 V supply. The CDR core and transceiver occupy 0.07 mm<SUP>2</SUP> and 0.94 mm<SUP>2</SUP>, respectively, in a 0.13 μm 1P8M CMOS process.</P>
Inhwa Jung,Gunok Jung,Janghoon Song,Moo-Young Kim,Junyoung Park,Sung Bae Park,Chulwoo Kim IEEE 2008 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.55 No.2
<P>Portable multiphase clock generators capable of adjusting its clock phase according to input clock frequencies have been developed both in a 0.18-mum and in a 0.13-mum CMOS technologies. They consist of a full-digital CMOS circuit design that leads to a simple, robust, and portable IP. In addition, their open-loop architecture lead to no jitter accumulation and one-cycle lock characteristic that enables clock-on-demand circuit structures. The implemented low power clock generator tile in a 0.13-mum CMOS technology occupies only 0.004 mm <SUP>2</SUP> and operates at variable input frequencies ranging from 625 MHz to 1.2 GHz within a plusmn 2% phase error having one-cycle lock time.</P>
Self-impedance calibrated PVT-insensitive pseudo open drain output driver without external resistors
Junyoung Song,Inhwa Jung,Sewook Hwang,Chulwoo Kim IET 2012 Electronics letters Vol.48 No.22
<P>Proposed is a pseudo open drain output driver without external resistors. The resistance variation detector can reduce the cost and space of external resistors. The PVT variation detector is able to sense process, voltage and temperature conditions. The on-die termination impedance is constantly matched in response to the resistance, process, voltage and temperature conditions. The overall circuit occupies 0.126 mm<SUP>2</SUP> and consumes 5.58 mW, and the circuit is implemented in 0.18 m CMOS technology.</P>
Piecewise Linear Modulation Technique for Spread Spectrum Clock Generation
Minyoung Song,Sunghoon Ahn,Inhwa Jung,Yongtae Kim,Chulwoo Kim IEEE 2013 IEEE transactions on very large scale integration Vol.21 No.7
<P>We propose a novel modulation profile for a spread spectrum clock generator (SSCG). The proposed piecewise linear (PWL) modulation profile significantly reduces electromagnetic interference with a simple implementation. Two SSCGs with two- and three-slope-PWL modulation profiles are used. Both SSCGs consist of the proposed spread spectrum control profile generator and a phase-locked loop that includes a high-resolution fractional divider to reduce quantization noise from a delta-sigma modulator. The SSCG with the two-slope-PWL modulation profile was fabricated in a 0.18 μm 1P4M CMOS technology. The measured peak power reduction level of the two-slope-PWL modulation profile is 14.2 dB with 5000 ppm down spreading at 1.5 GHz. The SSCG occupies an active area of 0.49 mm<SUP>2</SUP> and consumes 40 mW of power at 1.5 GHz. The SSCG with the three-slope-PWL modulation profile was fabricated in a 0.13 μm 1P6M CMOS technology. The measured peak power reduction level of the three-slope-PWL modulation profile is 10.3 and 10.52 dB with 5000 ppm down spreading at 162 and 270 MHz, respectively. The SSCG occupies an active area of 0.096 mm<SUP>2</SUP> and dissipates 1 mW of power at 270 MHz.</P>
Shin, Gunchul,Jung, Inhwa,Malyarchuk, Viktor,Song, Jizhou,Wang, Shuodao,Ko, Heung Cho,Huang, Yonggang,Ha, Jeong Sook,Rogers, John A. WILEY-VCH Verlag 2010 Small Vol.6 No.7
<P>The fabrication of a hemispherical electronic-eye camera with optimized designs based upon micromechanical analysis is reported. The photodetector arrays combine layouts with multidevice tiles and extended, non-coplanar interconnects to improve the fill factor and deformability, respectively. Quantitative comparison to micromechanics analysis reveals the key features of these designs. Color images collected with working cameras demonstrate the utility of these approaches.</P> <B>Graphic Abstract</B> <P>The fabrication of a hemispherical electronic-eye camera with optimized designs based upon micromechanical analysis is reported. The photodetector arrays combine layouts with multidevice tiles and extended, non-coplanar interconnects to improve the fill factor and deformability, respectively. <img src='wiley_img_2010/16136810-2010-6-7-SMLL200901350-content.gif' alt='wiley_img_2010/16136810-2010-6-7-SMLL200901350-content'> </P>
A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile
Sewook Hwang,Minyoung Song,Young-Ho Kwak,Inhwa Jung,Chulwoo Kim IEEE 2012 IEEE journal of solid-state circuits Vol.47 No.5
<P>A frequency-locked loop (FLL) based spread-spectrum clock generator (SSCG) with a memoryless Newton-Raphson modulation profile is introduced in this paper. The SSCG uses an FLL as a main clock generator. It brings not only an area reduction to the SSCG but also the advantage of having multiple frequency deviations. A double binary-weighted DAC is proposed that modulates the frequency information of the frequency detector using a 1-1-1 MASH ΔΣ modulator. The Newton-Raphson mathematical algorithm is applied to the proposed profile generator in order to generate the optimized nonlinear profile without needing any memory, resulting in a reduction in the area and the power consumption. It also makes it possible to have multiple modulation frequencies. The SSCG can support 14 frequency deviations of ±0.5% to 3.5% in steps of 0.5% and three modulation frequencies of <I>f</I><SUB>m</SUB>, 2 <I>f</I><SUB>m</SUB> and 3 <I>f</I><SUB>m</SUB>. It achieved an EMI reduction of 19.14 dB with a 0.5% down spreading and a 31 kHz modulation frequency, while employing a core area of 0.076 mm<SUP>2</SUP> in a 0.13-μm CMOS process and consuming 23.72 mW at 3.5 GHz.</P>