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Junyoung Song,Sewook Hwang,Hyun-Woo Lee,Chulwoo Kim IEEE 2014 IEEE Transactions on Circuits and Systems II: Expr Vol. No.
<P>This brief proposes a 7.5-Gb/s transceiver with adaptive equalization and a bandwidth (BW)-shifting technique for ultrahigh-definition television. By applying dynamic preemphasis calibration and a BW-shifting phase-locked loop/clock and data recovery, the measured jitter of the output data with a 16.88-dB loss cable and clock are enhanced by 49.9% and 40%, respectively. In addition, a data-width-comparison-based adaptive equalizer with a self-adjusting reference voltage is proposed. With a 3.37-MHz sinusoidal jitter, the measured jitter tolerance of the proposed receiver is improved from 1.07UI to 2.97UI. The transmitter and the receiver consume 10.08 and 9.28 mW/Gb/s at 7.5 Gb/s, respectively, and occupy 0.14 and 0.15 mm<SUP>2</SUP>, respectively, using a 0.13- μm complementary metal-oxide-semiconductor process.</P>
Song, Junyoung,Hwang, Sewook,Lee, Hyun-Woo,Kim, Chulwoo IEEE 2018 IEEE transactions on circuits and systems. a publi Vol.65 No.1
<P>A 1-V 10-Gb/s/pin single-ended transceiver with a controllable active inductor-based output driver and adaptively calibrated cascaded-equalizer with infinite impulse response and finite impulse response filters for a post-LPDDR4 interface in a 65-nm CMOS technology is proposed. The proposed cascaded-equalizer removes the received long-tail inter symbol interference with the help of an IIR filter while the coefficients for the cascaded-equalizer are adaptively calibrated. In addition, the received single-ended ground-terminated data are converted to the differential pair by the proposed input buffer using a calibrated reference voltage. In the transmitter (TX), an output driver with controllable active inductors is proposed to reduce both power consumption and design complexity. At the maximum operating data rate, the measured power efficiencies of TX and receiver are 1.16 and 3.02 pJ/b, respectively, excluding the power dissipation of internal phase locked loop. In addition, the overall active area is 0.0091 mm<SUP>2</SUP>.</P>
Song, Junyoung,Hwang, Sewook,Kim, Chulwoo IEEE 2016 IEEE transactions on very large scale integration Vol.24 No.8
<P>A 4x5-Gb/s reference-less receiver is proposed in a 0.13-mu m CMOS technology. In the proposed reference-less clock and data recovery (CDR) circuit, asynchronous sampling-based frequency acquisition is proposed to achieve a fast frequency locking, and VCO calibration is proposed to attain a constant loop bandwidth. To reduce noise caused by multiple VCOs, a clock signal is forwarded from the main channel to the subchannels, and skews between the channels are compensated by a skew compensation algorithm. In the main channel, the reference-less CDR achieves a 1.12-mu s locking time, and the measured standard deviation of VCO gain is reduced from 0.33 to 0.08. The recovered clock jitter in the main channel is 1.591 ps(rms), and the power consumption of the main channel and the subchannels are 3.53 and 2.16 mW/Gb/s, respectively.</P>
Song, Junyoung,Lee, Hyun-Woo,Hwang, Sewook,Kim, Chulwoo IEEE 2017 IEEE transactions on very large scale integration Vol.25 No.1
<P>A 10 Gbits/s/pin graphics DRAM interface is developed in 65-nm CMOS technology. Several design techniques are proposed for high-speed operation in a noisy environment. A fast precharging data sampler guarantees high-speed sampling without the need for a decision feedback equalizer. In order to increase the data sampling margin, the PLL bandwidth is optimized depending on the system noises, which reduces the clock jitter by up to 55.1%. The crosstalk-induced jitter (CIJ) reduction technique suppresses the DQs jitter by employing the suggested training sequence for the GDDR5 interface. Pre- and de-emphasis are merged in one auxiliary driver. This chip operates at 10 Gbits/s/pin and exhibits a data eye opening of 0.78 UI with the CIJ reduction technique. The power consumptions of the TX and RX are 8.28 and 5.5 pJ/b/channel, respectively.</P>
( Junyoung Song ),( Taeyeon Won ),( Su Min Jo ),( Yang Dam Eo ),( Jin Sue Park ) 대한원격탐사학회 2021 大韓遠隔探査學會誌 Vol.37 No.4
This paper introduces a method of selecting priority update areas for subdivided land cover maps by training orthoimages and serial cadastral maps in a deep learning model. For the experiment, orthoimages and serial cadastral maps were obtained from the National Spatial Data Infrastructure Portal. Based on the VGG-16 model, 51,470 images were trained on 33 subdivided classifications within the experimental area and an accuracy evaluation was conducted. The overall accuracy was 61.42%. In addition, using the differences in the classification prediction probability of the misclassified polygon and the cosine similarity that numerically expresses the similarity of the land category features with the original subdivided land cover class, the cases were classified and the areas in which the boundary setting was incorrect and in which the image itself was determined to have a problem were identified as the priority update polygons that should be checked by operators.
Junyoung Song,Inhwa Jung,Minyoung Song,Young-Ho Kwak,Sewook Hwang,Chulwoo Kim IEEE 2013 IEEE transactions on circuits and systems. a publi Vol.60 No.2
<P>This paper proposes a 2.7 Gb/s referenceless transceiver with weighted PFD for frequency detection of random signals. A single loop referenceless CDR is also proposed to overcome the disadvantages of a dual loop CDR. The ANSI 8b/10b encoder & decoder with the scrambler, the serializer & de-serializer, and the output driver with pre-emphasis are included in the proposed transceiver architecture for DisplayPort v1.1a. The jitter of the generated clock at the Tx PLL is 3.28 ps<SUB>rms</SUB> at 2.7 Gb/s with 1.2 V supply. The eye opening of the transmitter output with 3 m cable is 0.54 UI. The measured jitter of the recovered clock at the CDR is 1.57 ps<SUB>rms</SUB>, and BER is less than 10<SUP>-12</SUP>. The receiver consumes 23 mW at 2.7 Gb/s with 1.2 V supply. The CDR core and transceiver occupy 0.07 mm<SUP>2</SUP> and 0.94 mm<SUP>2</SUP>, respectively, in a 0.13 μm 1P8M CMOS process.</P>
Junyoung Song,김민영,Kicheol Park,Hakil Lee 대한재활의학회 2012 Annals of Rehabilitation Medicine Vol.36 No.4
Objective To evaluate the safety and potential efficacy of “recombinant human growth hormone (rhGH)” on the functional recovery of completed stroke patients.Method Completed stroke patients were recruited. All participants were randomly assigned to the GH group (rhGH injection and rehabilitative therapy) or the control group (only rehabilitative therapy). Above all, they were closely monitored for safety. Further, for the efficacy measurement, Korean Modified Barthel Index (K-MBI), Manual Muscle strength Test (MMT), and Fugl-Meyer assessment (FMA) were assessed to determine the changes of functional recovery during 6-months of the study period. Along with it, diffusion tensor image was taken as the baseline, and a followed-up study to observe the changes in diffusion tensor tractography (DTT), during the period, and one patient in the GH group was also examined with functional MRI (fMRI). Index of fatigue on 5 point scale for the study period was also assessed.Results Twenty-two patients were enrolled, and 15 completed the study and were included in the analysis. No harmful adverse events were observed in the GH group. By comparison between the groups, the GH group showed more improvement in K-MBI than the control group (p<0.05). DTT showed less decrement of fibers in the GH group than in the control group, without statistical significance. fMRI showed an increment in the activated area. Patients in the GH group expressed no fatigue at all, during the study period (p=0.00).Conclusion The administration of rhGH in long term resulted in the improvement in K-MBI, and subjectively less tiredness during the injection period.
Self-impedance calibrated PVT-insensitive pseudo open drain output driver without external resistors
Junyoung Song,Inhwa Jung,Sewook Hwang,Chulwoo Kim IET 2012 Electronics letters Vol.48 No.22
<P>Proposed is a pseudo open drain output driver without external resistors. The resistance variation detector can reduce the cost and space of external resistors. The PVT variation detector is able to sense process, voltage and temperature conditions. The on-die termination impedance is constantly matched in response to the resistance, process, voltage and temperature conditions. The overall circuit occupies 0.126 mm<SUP>2</SUP> and consumes 5.58 mW, and the circuit is implemented in 0.18 m CMOS technology.</P>