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      • 과학기술계산을 위한 전자계산기용 특수 Library 개발에 관한 연구

        金相萬,姜承業,沈在洪,文東纘,徐光烈,洪勝弘,愼哲宰 광운대학교 1972 論文集 Vol.2 No.-

        In this paper the subroutine library of digital computer techniques to the solution of electronic networks problem are discussed. The application of digital-computer techniques to the solution of the integrations relating the terminal variables for linear time invariant inductos and capaciters are analyzed, then on the techniques of numerical integrations trapezoidal method is used. The subroutine library for differential equations and determinations which are used in electronic networks analysis have been developed. Since these programs are the general form, anybody can utilize the programs for his own purpose.

      • 마이크로波 인터디지탈 通過帶域

        愼哲宰 光云大學校 1975 論文集 Vol.4 No.-

        接地面에 공진기가 配列된 마이크로 波 인터디지탈 여파기에 대해 論했으며 Prototype에서 통과 대역으로서의 변화관계에 의한 설계식과 등가회로를 유도하였다. 이 설계식은 협대역이나 광대역 여파기에 적용될 수 있었다. 제작된 여파기는 매우 안전하나 이론 값보다도 실험에 의한 측정값은 약 10% 정도의 넓은 대역폭을 갖었다. The design of band-pass filters using interdigital arrays of resonators line elements between parallel ground planes is discussed. An approximate design equation which permit design directly from prototype filters are described. A design procedure will work for either narrow or wide band filters. Exact equivalent circuit from the impendance matrix using modern network synthesis techniques is derived the resulting filters are very compact and have strong stop bands with the second pass band centered at three times the center frequency of the first pass band. By experience, band width is 10% larger than is actually desired.

      • TTL 시뮬레이터의 콤파일러 設計에 關한 硏究

        愼哲宰,金容得 亞州大學校 1978 論文集 Vol.2 No.-

        本 論文에서는 特殊 目的의 小型 電子計算機를 單一 뻐스線 方法에 의한 TTL 集積回路로 設計하였으며, 各 指令語의 길이를 16비트로 構成함으로써 더욱 簡便한 콤파일러를 硏究하였다. 또한 本 實驗에서 160nsec의 基本 週期를 擇함으로써, TTL IC의 動作時間에 따른 最適値와 記憶素子의 악세스 타임이 같게 되었고, 構成 回路도 간단하게 만들어졌으며, 모든 프로그램도 만조하게 처리되었다. The special mini-computer was designed with the one-bus line systems employing the integrated circuits, and was studied by the method of easily making the compiler in 16 bits with each instruction fields. When the 160 nano seconds for a fundamental cycle were used, the optimum operating time for a TTL IC was egual to the access time for the main memory unit. As a result, the circuits were very simple, and the simulator functioned well for all the programs.

      • 食品中의 保存料 測定에 關한 硏究

        申秀澈,李在根 順天大學校 1982 論文集 Vol.1 No.1

        一般的으로 말해서 여러가지 種類의 食品속에 2개 이상의 食品添加物을 分析하는 것은 아주 복잡하고 어렵다. 그런데 gas chromatography법에 의한 效果的인 方法을 찾는 實驗을 하여 다음과 같은 結果를 얻었다. 1. 食品添加物의 抽出은 여러가지 食品에 적용할 수 있는 수증기 蒸溜로 하고, 이 抽出物은 dichloromethane에 吸收시켜 水溶性 狀態로 抽出하여 10%-FFAP column을 갖는 gas chromatography로 分析하는 것은 效果的인 方法으로 판명되었다. 內部標準物質로는 Fluorene이 使用되었고 retention time은 33分 정도로 적게 소요되었다. 2. 回收率 檢定實驗은 7가지 食品에 대하여 실시되었는데 83∼92% 정도였고 그중 SOA, IB-PHBA, P-PHBA의 回收率이 높았다. 그리고 食品에서는 빵, 된장, 간장에서 좋은 回收率을 보여 分離檢出이 잘 되었으며, 다른 여러가지 食品에도 널리 利用될 수 있는 것으로 생각된다. Generlly speaking, it would be difficult and much more complicated to analyze more than two had additives contained in the different kinds of food. But it was carried out the experiment to look for a desirable analyzing method by the "gas chromatography." The results are like followings 1. The extraction of food additives from foods was done by steam distillation which could be applied to many kinds of food. This extract was absorbed into the dichloromethane and extracted in aqueous phase. And it was proved that analyzing method of "gas chromatography" with 10% FFAP column was effective. Fluorene was used as Internal standard and retention time was about 33 minutes. 2. The recovery test of determinative was carried out for 7 foods and the recovery rates were from 83% to 92%. The recovery rates of SOA, IB-PHBA, P-PHBA were high. In foods, the recovery rates of bread, bean paste, Soy sauce were good. And food additives in these foods were well-seperated. and it is thought that the method can be used for the different kinds of food.

      • 멀티미디어 전송을 위한 무선가입자용 RF-모듈의 설계 및 제작

        김상태,신철재,Kim, Sang-Tae,Shin, Chull-Chai 한국전기전자학회 1999 전기전자학회논문지 Vol.3 No.2

        본 논문에서는 W-CDMA 이용한 10 [MHz]의 채널 대역폭을 갖는 다중채널 무선가입자망 단말기용 RF-모듈을 설계 제작하였다. RF-모듈은 송수신전단, 주파수합성기, 변복조기 및 전력제어회로로 구성하였다. 제작한 RF-모듈에 대한 시험결과 송신전력은 250 [mW], 통과대역내의 진폭과 위상왜곡을 측정한 전력의 평탄도는 ${\pm}1.5[dB]$를 얻었다. 또한 송신시 확산신호의 Chip Rate는 8.312 [Mcps]를 얻었고, 주파수합성기에 대한 측정결과는 RF 대역과 변복조를 위한 국부발진신호 주파수는 설계규격을 만족하였다. 수신전계강도특성과 AGC의 동작범위는 모두 60 [dB]로 만족하였고, RF-모듈과 기저대역과의 연동여부를 확인하기 위해 페이저도와 눈패턴을 측정한 결과 좋은 결과를 얻었다. In this paper, the RF-modules composed of front-end, frequency synthesizer, modulator/demodulator and power control multi channel WLL personal system for W-CDMA using 10 [MHz] RF channel bandwidth has been implemented and considered. The measured transmission power is 250 [mW] which is very close to the required value. The measured flatness of power at the final output stage is ${\pm}1.5[dB]$ over the required bandwidth of the receiver. In addition, it is found that the chip rate transmitting spread signal is set to 8.192 [MHz], the required rate. The frequencies of RF_LO signal and LO signal of the modulator and the demodulator measured by a frequency synthesizer are satisfied with design requirements. The operating range of the receiving strength signal indicator and AGC units shows 60 [dB] respectively. Also the measured phasor diagram and eye pattern for deciding the RF modules compatible with baseband digital signal processing part are shown good results.

      • Implementation of Pulse Shaping Filter for π/4-shift QPSK Modulator

        Young-kyun Kim,Min-Taig Kim,Chull-Chai Shin 한국정보과학회 1997 Journal of Electrical Engineering and Information Vol.2 No.1

        A pulse shaping filter for π/4-shift DQPSK modulator is implemented with less hardware complexity by utilizing the symmetry of premodulation digital filter and the feature of π/4-shift DQPSK modulation scheme. The proposed design gives significant reduction of memory size. The new method needs only 192 words of memory for 24-tap FIR filter, compared to the conventional method which consumes 16384 words of memory size. Moreover, as the number of FIR filter taps increases. the reduced amount of proposed method increases more and more, compared to the conventional method. A design for verification of proposed method with 32-tap FlR filter was implemented using only simple logic and 384 words of ROM plus a 8-bit adder.

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