http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
SangHak Shin,Sang-Don Byeon,Jeasang Song,Son Ngoc Truong,Hyun-Sun Mo,Deajeong Kim,Kyeong-Sik Min 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.6
In this paper, a new dynamic reference scheme is proposed to improve the read voltage margin better than the previous static reference scheme. The proposed dynamic reference scheme can be helpful in compensating not only the background pattern dependence but also the cell position dependence. The proposed dynamic reference is verified by simulating the CMOS-memristor hybrid circuit using the practical CMOS SPICE and memristor Verilog-A models. In the simulation, the percentage read voltage margin is compared between the previous static reference scheme and the new dynamic reference scheme. Assuming that the critical percentage of read voltage margin is 5%, the memristor array size with the dynamic scheme can be larger by 60%, compared to the array size with the static one. In addition, for the array size of 64 x 64, the interconnect resistance in the array with the dynamic scheme can be increased by 30% than the static reference one. For the array size of 128 x 128, the interconnect resistance with the proposed scheme can be improved by 38% than the previous static one, allowing more margin on the variation of interconnect resistance.
Shin, SangHak,Byeon, Sang-Don,Song, Jeasang,Truong, Son Ngoc,Mo, Hyun-Sun,Kim, Deajeong,Min, Kyeong-Sik The Institute of Electronics and Information Engin 2015 Journal of semiconductor technology and science Vol.15 No.6
In this paper, a new dynamic reference scheme is proposed to improve the read voltage margin better than the previous static reference scheme. The proposed dynamic reference scheme can be helpful in compensating not only the background pattern dependence but also the cell position dependence. The proposed dynamic reference is verified by simulating the CMOS-memristor hybrid circuit using the practical CMOS SPICE and memristor Verilog-A models. In the simulation, the percentage read voltage margin is compared between the previous static reference scheme and the new dynamic reference scheme. Assuming that the critical percentage of read voltage margin is 5%, the memristor array size with the dynamic scheme can be larger by 60%, compared to the array size with the static one. In addition, for the array size of $64{\times}64$, the interconnect resistance in the array with the dynamic scheme can be increased by 30% than the static reference one. For the array size of $128{\times}128$, the interconnect resistance with the proposed scheme can be improved by 38% than the previous static one, allowing more margin on the variation of interconnect resistance.
Age face simulation using aging functions on global and local features with residual images
Choi, Sung Eun,Jo, Jaeik,Lee, Sanghak,Choi, Heeseung,Kim, Ig-Jae,Kim, Jaihie Elsevier 2017 expert systems with applications Vol.80 No.-
<P><B>Abstract</B></P> <P>In many previous methods for facial age simulation, the shape and appearance features of Active Appearance Models (AAM) are widely used to model the global facial characteristics. However, they cannot sufficiently represent facial details such as spots, scars, fine wrinkles, and skin blemishes, because many of them are removed from the AAM features during the dimension reduction process. Therefore, previous methods are not suitable for real-world applications, such as forensics, face recognition, and entertainment production systems, which require more accurate and realistic age simulation. To overcome the limitation, this paper proposes an automatic age simulation method based on a synergetic combination of the residual image, local features, and AAM global features. The residual image, which is the difference between a facial image and its reconstructed image by using AAM features, contains facial details of the input image that are not included in the AAM features. Representation of facial details in the age simulation process is achieved by generating and adding a targeted age-weighted residual image to the facial image synthesized by the AAM features. Further, facial details such as wrinkles and skin blemishes that have not yet appeared at the current age but normally appear as aging proceeds, are supplemented, and represented by local features that show locally different aging characteristics. The experimental results show that the proposed method simulates a face more accurately and realistically than previous methods, thereby confirming that it is more suitable for the real-world applications.</P> <P><B>Highlights</B></P> <P> <UL> <LI> Age simulation method using global, local features and residual image is proposed. </LI> <LI> The residual image represents the personal characteristics of the input image. </LI> <LI> Local features represent the local aging characteristics of wrinkle and skin. </LI> </UL> </P>
Sangdon Byeon,Sanghak Shin,Jae-Sang Song,Son Ngoc Truong,Hyun-Sun Mo,Seongsoo Lee,Kyeong-Sik Min 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.5
For some low-frequency applications such as power-related circuits, NEM relays have been known to show better performance than MOSFETs. For example, in a step-down charge pump circuit, the NEM relays showed much smaller layout area and better energy efficiency than MOSFETs. However, severe process variations of NEM relays hinder them from being widely used in various low-frequency applications. To mitigate the process-variation problems of NEM relays, in this paper, a new NEMrelay charge pump circuit with the self-adjustment is proposed. By self-adjusting a pulse amplitude voltage according to process variations, the power consumption can be saved by 4.6%, compared to the conventional scheme without the self-adjustment. This power saving can also be helpful in improving the power efficiency of the proposed scheme. From the circuit simulation of NEM-relay charge pump circuit, the efficiency of the proposed scheme is improved better by 4.1% than the conventional.
Son Ngoc Truong,SangHak Shin,Sang-Don Byeon,JaeSang Song,Kyeong-Sik Min IEEE 2015 IEEE TRANSACTIONS ON NANOTECHNOLOGY Vol.14 No.6
<P>In this paper, we propose a new twin crossbar architecture of binary memristors for low-power image recognition. In the new twin crossbar, we use two identical memristor arrays instead of using the previous complementary memristor arrays of M<SUP>+</SUP> and M<SUP>-</SUP>. Thereby, we can apply the discrete cosine transform (DCT) algorithm to reduce the number of low-resistance state (LRS) cells in the two identical M<SUP>+</SUP> arrays. With the reduced number of LRS cells in two M<SUP>+</SUP> arrays, the power consumption in the crossbar can be significantly saved compared to the previous complementary crossbar that is not suitable to DCT. When the number of discarded coefficients in the DCT matrix is 56.25%, 67.19%, 76.56%, and 84.38%, the power consumption of the new twin crossbar is reduced by 51.7%, 61.3%, 69.9%, and 77.4%, respectively, compared to the previous complementary one.</P>