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Diwaker,Manoj Kumar Chaudhary,Praveen Tripathi,Ashutosh Bhatt,Abhay Saxena 보안공학연구지원센터 2016 International Journal of Software Engineering and Vol.10 No.12
Obtaining thematic maps using image classification techniques from hyperspectral datasets is a very difficult image processing task. In hyperspectral image analysis dimensionality reduction is one of the challenging pre-processing tasks, which is achieved using feature extraction techniques. The beauty of these techniques is that they drastically reduces the dimensionality of image and at the same time preserves the majority of the essential information. In this paper few most frequently used dimensionality reduction methods are being investigated, which helps to get accurateness. This research work presents a relative performance investigation of few mostly frequently used feature extraction techniques like Decision Boundary Feature Extraction (DBFE), Non-Parametric Weighted Feature Extraction (NWFE), Discriminative analysis feature extraction (DAFE) and Principal Component Analysis (PCA). The classification is carried out using two most widely used classification techniques including Gaussian Maximum Likelihood (GML) and neural network (NNs). The results obtained after performing experiments indicates that Decision Boundary Feature Extraction (DBFE) technique has provided the best accuracy among various investigated feature extraction techniques. The application areas of this research include areas like identification of exact location in battle field, drought affected areas, flooded areas and weather forecasting etc.
Rakhi Narang,Manoj Saxena,R. S. Gupta,Mridula Gupta 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.3
This work presents a comparative study of four Double Gate tunnel FET (DG-TFET) architectures: conventional p-i-n DG-TFET, p-n-p-n DG-TFET, a gate dielectric engineered Heterogate (HG) p-i-n DG-TFET and a new device architecture with the merits of both Hetero Gate and p-n-p-n, i.e. HG p-n-p-n DG-TFET. It has been shown that, the problem of high gate capacitance along with low ON current for a p-i-n TFET, which severely hampers the circuit performance of TFET can be overcome by using a p-n-p-n TFET with a dielectric engineered Hetero-gate architecture (i.e. HG p-n-p-n). P-n-p-n architecture improves the ON current and the heterogeneous dielectric helps in reducing the gate capacitance and suppressing the ambipolar behavior. Moreover, the HG architecture does not degrade the output characteristics, unlike the gate drain underlap architecture, and effectively reduces the gate capacitance.
Vandana Kumari,Manoj Saxena,R. S. Gupta,Mridula Gupta 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.6
The circuit level implementation of nanoscale Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET has been investigated and compared with the other conventional devices i.e. Insulated Shallow Extension (ISE) and Silicon On Nothing (SON) using the ATLAS 3D device simulator. It can be observed that ISE-SON based inverter shows better performance in terms of Voltage Transfer Characteristics, noise margin, switching current, inverter gain and propagation delay. The reliability issues of the various devices in terms of supply voltage, temperature and channel length variation has also been studied in the present work. Logic circuits (such as NAND and NOR gate) and ring oscillator are also implemented using different architectures to illustrate the capabilities of ISE-SON architecture for high speed logic circuits as compared to other devices. Results also illustrates that ISE-SON is much more temperature resistant than SON and ISE MOSFET. Hence, ISE-SON enables more aggressive device scaling for low-voltage applications.
Analytical Model of Double Gate MOSFET for High Sensitivity Low Power Photosensor
Rajni Gautam,Manoj Saxena,R. S.Gupta,Mridula Gupta 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.5
In this paper, a high-sensitivity low power photodetector using double gate (DG) MOSFET is proposed for the first time using change in subthreshold current under illumination as the sensitivity parameter. An analytical model for optically controlled double gate (DG) MOSFET under illumination is developed to demonstrate that it can be used as high sensitivity photodetector and simulation results are used to validate the analytical results. Sensitivity of the device is compared with conventional bulk MOSFET and results show that DG MOSFET has higher sensitivity over bulk MOSFET due to much lower dark current obtained in DG MOSFET because of its effective gate control. Impact of the silicon film thickness and gate stack engineering is also studied on sensitivity.
Vandana Kumari,Manoj Saxena,R. S. Gupta,Mridula Gupta 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.2
The impact of Empty Space layer in the channel region of a Double Gate (i.e. ESDG) MOSFET has been studied, by monitoring the DC, RF as well as the digital performance of the device using ATLAS 3D device simulator. The influence of temperature variation on different devices, i.e. Double Gate incorporating Empty Space (ESDG), Empty Space in Silicon (ESS), Double Gate (DG) and Bulk MOSFET has also been studied. The electrical performance of scaled ESDG MOSFET shows high immunity against Short Channel Effects (SCEs) and temperature variations. The present work also includes the linearity performance study in terms of VIP2 and VIP3. The proper bias point to get the higher linearity along with the higher transconductance and device gain has also been discussed.
Assessment of Ambipolar Behavior of a Tunnel FET and Influence of Structural Modifications
Rakhi Narang,Manoj Saxena,R. S. Gupta,Mridula Gupta 대한전자공학회 2012 Journal of semiconductor technology and science Vol.12 No.4
In the present work, comprehensive investigation of the ambipolar characteristics of two silicon (Si) tunnel field-effect transistor (TFET) architectures (i.e. p-i-n and p-n-p-n) has been carried out. The impact of architectural modifications such as heterogeneous gate (HG) dielectric, gate drain underlap (GDU) and asymmetric source/drain doping on the ambipolar behavior is quantified in terms of physical parameters proposed for ambipolarity characterization. Moreover, the impact on the miller capacitance is also taken into consideration since ambipolarity is directly related to reliable logic circuit operation and miller capacitance is related to circuit performance.
Assessment of Ambipolar Behavior of a Tunnel FET and Influence of Structural Modifications
Narang, Rakhi,Saxena, Manoj,Gupta, R.S.,Gupta, Mridula The Institute of Electronics and Information Engin 2012 Journal of semiconductor technology and science Vol.12 No.4
In the present work, comprehensive investigation of the ambipolar characteristics of two silicon (Si) tunnel field-effect transistor (TFET) architectures (i.e. p-i-n and p-n-p-n) has been carried out. The impact of architectural modifications such as heterogeneous gate (HG) dielectric, gate drain underlap (GDU) and asymmetric source/drain doping on the ambipolar behavior is quantified in terms of physical parameters proposed for ambipolarity characterization. Moreover, the impact on the miller capacitance is also taken into consideration since ambipolarity is directly related to reliable logic circuit operation and miller capacitance is related to circuit performance.
Kumari, Vandana,Saxena, Manoj,Gupta, R.S.,Gupta, Mridula The Institute of Electronics and Information Engin 2013 Journal of semiconductor technology and science Vol.13 No.2
The impact of Empty Space layer in the channel region of a Double Gate (i.e. ESDG) MOSFET has been studied, by monitoring the DC, RF as well as the digital performance of the device using ATLAS 3D device simulator. The influence of temperature variation on different devices, i.e. Double Gate incorporating Empty Space (ESDG), Empty Space in Silicon (ESS), Double Gate (DG) and Bulk MOSFET has also been studied. The electrical performance of scaled ESDG MOSFET shows high immunity against Short Channel Effects (SCEs) and temperature variations. The present work also includes the linearity performance study in terms of $VIP_2$ and $VIP_3$. The proper bias point to get the higher linearity along with the higher transconductance and device gain has also been discussed.
Analytical Model of Double Gate MOSFET for High Sensitivity Low Power Photosensor
Gautam, Rajni,Saxena, Manoj,Gupta, R.S.,Gupta, Mridula The Institute of Electronics and Information Engin 2013 Journal of semiconductor technology and science Vol.13 No.5
In this paper, a high-sensitivity low power photodetector using double gate (DG) MOSFET is proposed for the first time using change in subthreshold current under illumination as the sensitivity parameter. An analytical model for optically controlled double gate (DG) MOSFET under illumination is developed to demonstrate that it can be used as high sensitivity photodetector and simulation results are used to validate the analytical results. Sensitivity of the device is compared with conventional bulk MOSFET and results show that DG MOSFET has higher sensitivity over bulk MOSFET due to much lower dark current obtained in DG MOSFET because of its effective gate control. Impact of the silicon film thickness and gate stack engineering is also studied on sensitivity.
Narang, Rakhi,Saxena, Manoj,Gupta, R.S.,Gupta, Mridula The Institute of Electronics and Information Engin 2013 Journal of semiconductor technology and science Vol.13 No.3
This work presents a comparative study of four Double Gate tunnel FET (DG-TFET) architectures: conventional p-i-n DG-TFET, p-n-p-n DG-TFET, a gate dielectric engineered Heterogate (HG) p-i-n DG-TFET and a new device architecture with the merits of both Hetero Gate and p-n-p-n, i.e. HG p-n-p-n DG-TFET. It has been shown that, the problem of high gate capacitance along with low ON current for a p-i-n TFET, which severely hampers the circuit performance of TFET can be overcome by using a p-n-p-n TFET with a dielectric engineered Hetero-gate architecture (i.e. HG p-n-p-n). P-n-p-n architecture improves the ON current and the heterogeneous dielectric helps in reducing the gate capacitance and suppressing the ambipolar behavior. Moreover, the HG architecture does not degrade the output characteristics, unlike the gate drain underlap architecture, and effectively reduces the gate capacitance.