RISS 학술연구정보서비스

검색
다국어 입력

http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.

변환된 중국어를 복사하여 사용하시면 됩니다.

예시)
  • 中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
  • 北京 을 입력하시려면 beijing을 입력하시고 space를 누르시면 됩니다.
닫기
    인기검색어 순위 펼치기

    RISS 인기검색어

      KCI등재 SCIE SCOPUS

      Assessment of Ambipolar Behavior of a Tunnel FET and Influence of Structural Modifications

      한글로보기

      https://www.riss.kr/link?id=A99655087

      • 0

        상세조회
      • 0

        다운로드
      서지정보 열기
      • 내보내기
      • 내책장담기
      • 공유하기
      • 오류접수

      부가정보

      다국어 초록 (Multilingual Abstract)

      In the present work, comprehensive investigation of the ambipolar characteristics of two silicon (Si) tunnel field-effect transistor (TFET) architectures (i.e. p-i-n and p-n-p-n) has been carried out. The impact of architectural modifications such as ...

      In the present work, comprehensive investigation of the ambipolar characteristics of two silicon (Si) tunnel field-effect transistor (TFET) architectures (i.e. p-i-n and p-n-p-n) has been carried out. The impact of architectural modifications such as heterogeneous gate (HG) dielectric, gate drain underlap (GDU) and asymmetric source/drain doping on the ambipolar behavior is quantified in terms of physical parameters proposed for ambipolarity characterization. Moreover, the impact on the miller capacitance is also taken into consideration since ambipolarity is directly related to reliable logic circuit operation and miller capacitance is related to circuit performance.

      더보기

      목차 (Table of Contents)

      • Abstract
      • Ⅰ. INTRODUCTION
      • Ⅱ. DEVICE ARCHITECTURE DESCRIPTION AND SIMULATION
      • Ⅲ. FORMULATION OF AMBIPOLAR CHARACTERISTIC PARAMETER
      • Ⅳ. IMPACT OF STRUCTURAL MODIFICATIONS
      • Abstract
      • Ⅰ. INTRODUCTION
      • Ⅱ. DEVICE ARCHITECTURE DESCRIPTION AND SIMULATION
      • Ⅲ. FORMULATION OF AMBIPOLAR CHARACTERISTIC PARAMETER
      • Ⅳ. IMPACT OF STRUCTURAL MODIFICATIONS
      • Ⅴ. COMBINATIONAL CIRCUIT OPERATION AND IMPACT OF AMBIPOLARITY
      • Ⅴ. CONCLUSIONS
      • ACKNOWLEDGMENTS
      • REFERENCES
      더보기

      참고문헌 (Reference)

      1 A. Tura, "Vertical Silicon p-n-p-n Tunnel nMOSFET With MBE-Grown Tunneling Junction" 58 (58): 1907-1913, 2011

      2 이성주, "Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (<= 50 mV/decade) at Room Temperature" IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC 32 (32): 437-439, 201104

      3 W. Y. Choi, "Tunneling field-effect transistors (TFETs) withsubthreshold swing (SS) less than 60 mV/dec" 28 (28): 743-745, 2007

      4 Y. Yang, "Tunneling field-effect transistor: capacitance components and modeling" 31 (31): 752-754, 2010

      5 A. S. Verhulst, "Tunnel field-effect transistor without gate-drain overlap" 91 : 053102-, 2007

      6 W. G. Vandenderghe, "Tunnel Field-Effect Transistor With Gated Tunnel Barrier"

      7 V. Nagavarapu, "The Tunnel Source (PNPN) n MOSFET: A Novel High Performance Transistor" 55 (55): 1013-1019, 2008

      8 Adkisson, "Lateral Diffusion field effect transistor with asymmetric gate dielectric profile"

      9 W. Y. Choi, "Hetero-Gate-Dielectric Tunneling Field-Effect Transistors" 57 (57): 2317-2319, 2010

      10 S. Mookerjea, "Effective Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation" 56 (56): 2092-2098, 2009

      1 A. Tura, "Vertical Silicon p-n-p-n Tunnel nMOSFET With MBE-Grown Tunneling Junction" 58 (58): 1907-1913, 2011

      2 이성주, "Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (<= 50 mV/decade) at Room Temperature" IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC 32 (32): 437-439, 201104

      3 W. Y. Choi, "Tunneling field-effect transistors (TFETs) withsubthreshold swing (SS) less than 60 mV/dec" 28 (28): 743-745, 2007

      4 Y. Yang, "Tunneling field-effect transistor: capacitance components and modeling" 31 (31): 752-754, 2010

      5 A. S. Verhulst, "Tunnel field-effect transistor without gate-drain overlap" 91 : 053102-, 2007

      6 W. G. Vandenderghe, "Tunnel Field-Effect Transistor With Gated Tunnel Barrier"

      7 V. Nagavarapu, "The Tunnel Source (PNPN) n MOSFET: A Novel High Performance Transistor" 55 (55): 1013-1019, 2008

      8 Adkisson, "Lateral Diffusion field effect transistor with asymmetric gate dielectric profile"

      9 W. Y. Choi, "Hetero-Gate-Dielectric Tunneling Field-Effect Transistors" 57 (57): 2317-2319, 2010

      10 S. Mookerjea, "Effective Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation" 56 (56): 2092-2098, 2009

      11 K. Boucart, "Double-Gate Tunnel FET With High-κ Gate Dielectric" 54 (54): 1725-1733, 2007

      12 T. Krishnamohan, "Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) with record high drive currents and<<60mV/dec subthreshold slope" 1-3, 2008

      13 J. Zhuge, "Digital-circuit analysis of short-gate tunnel FETs for low-voltage applications" 26 : 085001-085008, 2011

      14 Seongjae Cho, "Design Optimization of a Type‐I Heterojunction Tunneling Field‐Effect Transistor (I‐HTFET) for High Performance Logic Technology" 대한전자공학회 11 (11): 182-189, 2011

      15 M. Masahara, "Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope" 28 (28): 217-219, 2007

      16 K. E. Moselund, "Comparison of VLS grown Si NW tunnel FETs with different gate stacks" 448-451, 2009

      17 S. Mookerjea, "Comparative Study of Si, Ge and InAs Based Steep Subthreshold Slope Tunnel Transistors for 0.25V Supply Voltage Logic Applications" 47-48, 2008

      18 이성주, "CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With <= 50-mV/decade Subthreshold Swing" IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC 32 (32): 1504-1506, 201111

      19 Hraziia, "An analysis on the ambipolar current in Si double-gate tunnel FETs" 70 : 67-72, 2012

      20 Jung-Shik Jang, "Ambipolarity Factor of Tunneling Field-Effect Transistors (TFETs)" 대한전자공학회 11 (11): 272-277, 2011

      21 J. -S. Jang, "Ambipolarity Characterization of Tunneling Field-Effect Transistors" 1-2, 2010

      22 "ATLAS User’s guide, SILVACO International, Version 5.14.0.R"

      23 J. Singh, "A novel Si- Tunnel FET based SRAM design for ultra lowpower 0.3V VDD applications" 181-186, 2010

      더보기

      동일학술지(권/호) 다른 논문

      동일학술지 더보기

      더보기

      분석정보

      View

      상세정보조회

      0

      Usage

      원문다운로드

      0

      대출신청

      0

      복사신청

      0

      EDDS신청

      0

      동일 주제 내 활용도 TOP

      더보기

      주제

      연도별 연구동향

      연도별 활용동향

      연관논문

      연구자 네트워크맵

      공동연구자 (7)

      유사연구자 (20) 활용도상위20명

      인용정보 인용지수 설명보기

      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2023 평가예정 해외DB학술지평가 신청대상 (해외등재 학술지 평가)
      2020-01-01 평가 등재학술지 유지 (해외등재 학술지 평가) KCI등재
      2014-01-21 학회명변경 영문명 : The Institute Of Electronics Engineers Of Korea -> The Institute of Electronics and Information Engineers KCI등재
      2010-11-25 학술지명변경 한글명 : JOURNAL OF SEMICONDUTOR TECHNOLOGY AND SCIENCE -> JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE KCI등재
      2010-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      2009-01-01 평가 등재후보 1차 PASS (등재후보1차) KCI등재후보
      2007-01-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
      더보기

      학술지 인용정보

      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.42 0.13 0.35
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.3 0.29 0.308 0.03
      더보기

      이 자료와 함께 이용한 RISS 자료

      나만을 위한 추천자료

      해외이동버튼