1 A. Tura, "Vertical Silicon p-n-p-n Tunnel nMOSFET With MBE-Grown Tunneling Junction" 58 (58): 1907-1913, 2011
2 이성주, "Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (<= 50 mV/decade) at Room Temperature" IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC 32 (32): 437-439, 201104
3 W. Y. Choi, "Tunneling field-effect transistors (TFETs) withsubthreshold swing (SS) less than 60 mV/dec" 28 (28): 743-745, 2007
4 Y. Yang, "Tunneling field-effect transistor: capacitance components and modeling" 31 (31): 752-754, 2010
5 A. S. Verhulst, "Tunnel field-effect transistor without gate-drain overlap" 91 : 053102-, 2007
6 W. G. Vandenderghe, "Tunnel Field-Effect Transistor With Gated Tunnel Barrier"
7 V. Nagavarapu, "The Tunnel Source (PNPN) n MOSFET: A Novel High Performance Transistor" 55 (55): 1013-1019, 2008
8 Adkisson, "Lateral Diffusion field effect transistor with asymmetric gate dielectric profile"
9 W. Y. Choi, "Hetero-Gate-Dielectric Tunneling Field-Effect Transistors" 57 (57): 2317-2319, 2010
10 S. Mookerjea, "Effective Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation" 56 (56): 2092-2098, 2009
1 A. Tura, "Vertical Silicon p-n-p-n Tunnel nMOSFET With MBE-Grown Tunneling Junction" 58 (58): 1907-1913, 2011
2 이성주, "Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (<= 50 mV/decade) at Room Temperature" IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC 32 (32): 437-439, 201104
3 W. Y. Choi, "Tunneling field-effect transistors (TFETs) withsubthreshold swing (SS) less than 60 mV/dec" 28 (28): 743-745, 2007
4 Y. Yang, "Tunneling field-effect transistor: capacitance components and modeling" 31 (31): 752-754, 2010
5 A. S. Verhulst, "Tunnel field-effect transistor without gate-drain overlap" 91 : 053102-, 2007
6 W. G. Vandenderghe, "Tunnel Field-Effect Transistor With Gated Tunnel Barrier"
7 V. Nagavarapu, "The Tunnel Source (PNPN) n MOSFET: A Novel High Performance Transistor" 55 (55): 1013-1019, 2008
8 Adkisson, "Lateral Diffusion field effect transistor with asymmetric gate dielectric profile"
9 W. Y. Choi, "Hetero-Gate-Dielectric Tunneling Field-Effect Transistors" 57 (57): 2317-2319, 2010
10 S. Mookerjea, "Effective Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation" 56 (56): 2092-2098, 2009
11 K. Boucart, "Double-Gate Tunnel FET With High-κ Gate Dielectric" 54 (54): 1725-1733, 2007
12 T. Krishnamohan, "Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) with record high drive currents and<<60mV/dec subthreshold slope" 1-3, 2008
13 J. Zhuge, "Digital-circuit analysis of short-gate tunnel FETs for low-voltage applications" 26 : 085001-085008, 2011
14 Seongjae Cho, "Design Optimization of a Type‐I Heterojunction Tunneling Field‐Effect Transistor (I‐HTFET) for High Performance Logic Technology" 대한전자공학회 11 (11): 182-189, 2011
15 M. Masahara, "Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope" 28 (28): 217-219, 2007
16 K. E. Moselund, "Comparison of VLS grown Si NW tunnel FETs with different gate stacks" 448-451, 2009
17 S. Mookerjea, "Comparative Study of Si, Ge and InAs Based Steep Subthreshold Slope Tunnel Transistors for 0.25V Supply Voltage Logic Applications" 47-48, 2008
18 이성주, "CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With <= 50-mV/decade Subthreshold Swing" IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC 32 (32): 1504-1506, 201111
19 Hraziia, "An analysis on the ambipolar current in Si double-gate tunnel FETs" 70 : 67-72, 2012
20 Jung-Shik Jang, "Ambipolarity Factor of Tunneling Field-Effect Transistors (TFETs)" 대한전자공학회 11 (11): 272-277, 2011
21 J. -S. Jang, "Ambipolarity Characterization of Tunneling Field-Effect Transistors" 1-2, 2010
22 "ATLAS User’s guide, SILVACO International, Version 5.14.0.R"
23 J. Singh, "A novel Si- Tunnel FET based SRAM design for ultra lowpower 0.3V VDD applications" 181-186, 2010