A Wideband Receiver Front-End Employing New Fine RF Gain Control Driven by Frequency-Translated Impedance Property

Kuduck Kwon,Junghwan Han,Ilku Nam THE INSTITUTE OF ELECTRICAL ENGINEERS 2015 IEEE Microwave and Wireless Components Letters Vol. No.

<P>A new gain control methodology employing frequency-translated (FT) impedance property is proposed for RF amplifiers. By adaptively controlling the baseband impedance through the FT property, fine RF gain control can be achieved without degradation in the RF characteristics such as noise figure (NF), gain, input matching, and bandwidth. To verify the proposed method, a wideband receiver (RX) front-end (FE) with the fine RF gain control has been designed for 2G/3G/4G cellular applications. The implemented RX FE consists of a wideband capacitor cross-coupled common-gate low-noise amplifier, a 25% duty cycle passive mixer with baseband impedance array, a baseband transconductor with variable input capacitance, and a trans-impedance amplifier. The RX FE was fabricated in a 65 nm CMOS process. It has a conversion gain from 26 dB to 42 dB with 1 dB gain resolution, and achieves a minimum NF lower than 3.3 dB, out-of-band IIP3 of -2 dBm, and IIP2 of more than 56 dBm. It draws an average current of 14.8 mA from a 1.2 V supply voltage.</P>

A 23.4 mW 68 dB Dynamic Range Low Band CMOS Hybrid Tracking Filter for ATSC Digital TV Tuner Adopting RC and Gm-C Topology

Kuduck Kwon,Kwyro Lee IEEE 2011 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.58 No.10

<P>In this paper, a 48-200 MHz CMOS hybrid tracking low-pass filter with low power and high dynamic range is presented to solve a local oscillator harmonic-mixing problem for Advanced Television Systems Committee terrestrial digital TV tuner integrated circuits. For low power consumption, the first-order passive RC filter and the second-order transconductor-C filter are combined to implement the third-order Chebyshev tracking low-pass filter. A transconductor linearization technique based on a method of multiple gated transistors is adopted to achieve high dynamic range. Fabricated in a 0.18 μm CMOS process, it achieves a maximum in-band input-referred noise density of 5.1 nV/√Hz and maximum in-band output-referred third-order intercept point of 17.3 dBm, while dissipating 23.4 mW with 1.8 V. The total chip area is 0.6 mm × 0.4 mm.</P>

Design methodology of baseband analog chain to maximize a spurious free dynamic range for ATSC terrestrial and cable digital TV tuner

Kuduck Kwon,Hong-Teuk Kim,Kwyro Lee IEEE 2008 IEEE TRANSACTIONS ON CONSUMER ELECTRONICS - Vol.54 No.2

<P>This paper presents a fully integrated tunable CMOS baseband analog (BBA) chain optimized for advanced television systems committee (ATSC) terrestrial and cable digital TV tuner integrated circuits (ICs). To maximize the spurious free dynamic range (SFDR) of the BBA chain for both standards, the design guideline is introduced with respect to the optimized allocation of the gain of each block. The bandwidth is selectable from 3 MHz, 3.5 MHz, or 4 MHz. Fabricated in a 0.18-mum CMOS process, it provides a minimum input referred noise density of 15.5 nV/radic(Hz) with 62 dB gain and out-of-channel output referred third-order intercept point (OIP3) of 33 dBm, while it drains an average current of 89 mA from 3.3 V. The total chip area is 1 mm times 1.2 mm.</P>

A 50–300-MHz Highly Linear and Low-Noise CMOS <tex> $Gm{\hbox{-}}C$</tex> Filter Adopting Multiple Gated Transistors for Digital TV Tuner ICs

Kuduck Kwon,Hong-Teuk Kim,Kwyro Lee IEEE 2009 IEEE transactions on microwave theory and techniqu Vol.57 No.2

<P>In this paper, a highly linear and low noise CMOS active tracking low-pass filter is presented to overcome a local oscillator harmonic mixing problem for Advanced Television Systems Committee terrestrial and cable digital TV tuner integrated circuits. A transconductor linearization technique based on a method of multiple gated transistors is adopted to improve the linearity performance. The cutoff frequency of the proposed filter is tunable from 50 to 300 MHz. Fabricated in a 0.18-mum CMOS process, the filter provides a minimum input referred noise density of 5 nV/radic(Hz) and maximum in-band output referred third-order intercept point of 16.9 dBm, while drawing an average current of 40 mA from 1.8 V. The total chip area is 1 mm times 0.9 mm.</P>

A Hybrid Transformer-Based CMOS Duplexer With a Single-Ended Notch-Filtered LNA for Highly Integrated Tunable RF Front-Ends

Kwon, Kuduck,Kim, Sinyoung,Son, Ki Yong THE INSTITUTE OF ELECTRICAL ENGINEERS 2018 Vol. No.

<P>A hybrid transformer-based CMOS tunable duplexer with a single-ended blocker-tolerant low-noise amplifier (LNA) is proposed for a highly integrated reconfigurable RF front-end architecture. The proposed LNA adopts <TEX>$Q$</TEX>-enhanced <TEX>$LC$</TEX> notch filter at the source of the cascode device and <TEX>$LC$</TEX> bandpass filter at the load. It improves the blocker tolerance and linearity of the receiver by rejecting unwanted out-of-band blockers and transmitter (TX) leakage signals. The duplexer with the notch-filtered LNA was fabricated in a 65-nm CMOS process. It has a voltage gain of 24.2 dB from the antenna to the LNA output with 28-dB notch filtering, cascaded noise figure of 6.4 dB, TX insertion loss of 3.8 dB, and IIP3<SUB>FD</SUB> of 52.4 dBm. It can also cover a mid-band range from 1.6 to 2.2 GHz in cellular applications. It draws an average current of 8 mA from a supply voltage of 1.2 V and has an active area of 1.19 mm<SUP>2</SUP>.</P>

A Three-Terminal n+-p-n+ Silicon CMOS Light-Emitting Device for the New Fully Integrated Optical-Type Fingerprint Recognition System

Kuduck Kwon,Ilku Nam,Kwyro Lee IEEE 2016 Journal of display technology Vol.12 No.1

<P>A new fully integrated CMOS optical-type fingerprint recognition system with silicon light-emitting devices (LEDs) and photodiodes is proposed. A three-terminal n+-p-n+ silicon CMOS LED is designed and implemented as a key block to replace the bulky optical light source and to realize a slim and integrated fingerprint sensor. The proposed LED employs injection-enhanced silicon in an avalanche mode, where E-field confinement with a wedge shape at a reverse biased p-n+ junction and hot-carrier injection from the adjacent forward biased p-n+ junction are applied to increase the quantum conversion efficiency of the LED. The developed LED was fabricated in a 0.18 mu m CMOS process. It emits 1.27 nW at a 600 nm wavelength consuming 2 mA at a 0.5 V reverse biased voltage and 2 V forward biased voltage. It provides an electrical-to-optical power conversion efficiency of 1.27 x 10(-6).</P>

Sub-6 GHz Noise-cancelling Balun-LNTA with Dualband Q-enhanced LC Notch Filter for 5G New Radio Cellular Applications

Donggu Lee,Kuduck Kwon 대한전자공학회 2022 Journal of semiconductor technology and science Vol.22 No.3

This paper presents a blocker-tolerant broadband balun-low-noise transconductance amplifier (LNTA) with a high-Q dual-band LC notch filter for 5G new radio (NR) sub-6GHz cellular applications. The proposed balun-LNTA employs a noise-cancelling 1:5 CG-CS balun-LNA topology with local feedback gm-boosting and modified currentbleeding techniques to support entire bands of sub-6 GHz 5G NR application with less than 5 dB NF performance and balanced output of balun-LNTA. The dual-band Q-boosted LC notch filter with a bandswitchable differential inductor is also proposed to enhance blocker tolerance of the receiver by removing out-of-band blockers and strong transmitter leakage signals. Simulated in a 65-nm CMOS process, the designed balun-LNTA achieves a minimum noise figure of 2.38 dB, a maximum transconductance gain of 44 mS, an S11 of less than ‒10 dB over the frequency range of 50 MHz-6 GHz, an input-referred third-order intercept point of 1.82 dBm, and blocker rejection ratios of more than 15 dB. It consumes 5.9 mA from a nominal supply voltage of 1 V. Its active die area is 0.55 mm2.

A 50-MHz–1-GHz 2.3-dB NF Noise-Cancelling Balun-LNA Employing a Modified Current-Bleeding Technique and Balanced Loads

Kim, Sinyoung,Kwon, Kuduck IEEE 2019 IEEE Transactions on Circuits and Systems I: Regul Vol.66 No.2

<P>A new noise-cancelling method that employs a modified current-bleeding (CBLD) technique and balanced loads is presented by developing a design for a low-noise and high-linearity balun-low-noise amplifier (LNA) for broadband applications. The basic common-gate (CG)–common-source (CS) balun topology cannot achieve a noise figure (NF) of less than 3 dB. Thus, a practical topology containing a CS transistor of which the transconductance is N times larger than that of the CG transistor and a CS resistor of which the resistance is <TEX>$N$</TEX> times smaller than that of the CG resistor is often used to decrease the NF. However, unsymmetrical load resistors cause a gain and phase imbalance at the differential output. The proposed modified CBLD technique enables the balun-LNA to achieve differential balanced output, low noise, and low-second-order distortion characteristics. The proposed balun-LNA is implemented in 65-nm CMOS technology and covers the frequency range of 50 MHz–1 GHz. It achieves a voltage gain of 30 dB, an S11 of less than −10 dB, an OIP3 of 25.9 dBm, and an OIP2 of 50.6 dBm. The minimum NF is 2.3 dB whereas the average NF is 2.63 dB across the whole band. It operates at a nominal supply voltage of 2.2 V with bias currents of 9 mA. The active die area is 0.0448 mm<SUP>2</SUP>.</P>

CMOS Tunable Channel-selection LNA Employing Active Feedback Technique and Gain-boosted N-path Bandpass Filter for Advanced Cellular Applications

Donggu Lee,Kuduck Kwon 대한전자공학회 2020 Journal of semiconductor technology and science Vol.20 No.5

In this paper, a CMOS tunable channel-selection low-noise amplifier (LNA) that employs an active feedback technique and gain-boosted N-path bandpass filter (BPF) is presented for advanced cellular applications. The proposed LNA achieves broadband input power matching and low noise figure (NF) performance by using the active feedback technique. The gain-boosted N-path BPF is also used to implement a high-Q RF fourth-order bandpass filtering. Simulated in a 65-nm CMOS process, the proposed LNA achieves a maximum voltage gain of 17 dB, minimum NF of 2.16 dB, maximum out-of-band blocker rejection ratio of 21 dB at 80 MHz offset frequency. The center-frequency tuning range of the LNA is 0.1 ‒ 4 GHz, which includes all FDD bands in the 3G/4G/5G sub-6 GHz cellular standards. It draws a DC bias current of 21 mA from a supply voltage of 1.2 V. The active die area is 0.8 mm2.

A 2.4-GHz Low-power Low-IF Receiver Employing a Quadrature Low-noise Amplifier for Bluetooth Low Energy Applications

Beomyu Park,Kuduck Kwon 대한전자공학회 2020 Journal of semiconductor technology and science Vol.20 No.5

In this paper, a low-power low-IF receiver employing a quadrature low-noise amplifier (LNA) is proposed for Bluetooth low energy (BLE) applications. The proposed quadrature LNA, which can provide accurate quadrature signals in the RF path, consists of a common-source amplifier with inductive degeneration and a quadrature generator based on a common-gate amplifier with a single RC network. Therefore, a BLE receiver using the proposed LNA can eliminate quadrature generating circuitry of the LO chain, thereby reducing power consumption. The implemented receiver is composed of the quadrature LNA, single-to-differential double-balanced active mixer, and second-order Gm-C complex filter. Simulated in a 65-nm CMOS process, it achieves a conversion gain, noise figure, and an image rejection ratio of 53.2 dB, 4.81 dB and 38 dB, respectively, and consumes 2.2 mA from a supply voltage of 0.8 V. The die area is 2.24 mm2.