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Atsushi Izukura,Akio Tsuneda,Takahiro Inoue 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
We present several test patterns generated by simple deterministic algorithms for digital logic testing of LSIs. The proposed algorithms are based on bit-flipping of patterns. We evaluated the test lengths for covering 95% of the rate of faults and compare it with linear feedback shift registers (LFSRs) which are extensively used as test pattern generators, where ISCAS’85 benchmark circuits are used.