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RISS 인기검색어
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- 주제어 : reverse bias leakage current (검색결과 5 건)
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Reverse Bias Leakage Current Mechanism of AlGaN/InGaN/GaN Heterostructure
Apurba Chakraborty,Saptarsi Ghosh,Partha Mukhopadhyay,Sanjay K. Jana,Syed Mukulika Dinara,Ankush Bag,Mihir K. Mahata,Rahul Kumar,Subhashis Das,Palash Das,Dhrubes Biswas 대한금속·재료학회 2016 ELECTRONIC MATERIALS LETTERS Vol.12 No.2
The reverse bias leakage current mechanism of AlGaN/InGaN/GaNheterostructure is investigated by current-voltage measurement intemperature range from 298 K to 423 K. The Higher electric field acrossthe AlGaN barrier layer of AlGaN/InGaN/GaN double heterostructuredue to higher polarization charge is found to be responsible for strongFowler-Nordheim (FN) tunnelling in the electric field higher than3.66 MV/cm. For electric field less than 3.56 MV/cm, the reverse biasleakage current is also found to follow the trap assisted Frenkel-Poole(FP) emission in low negative bias region. Analysis of reverse FPemission yielded the barrier height of trap energy level of 0.34 eV withrespect to Fermi level.
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Introduction to Industrial Applications of Low Power Design Methodologies
Kim, Hyung-Ock,Lee, Bong-Hyun,Choi, Jung-Yon,Won, Hyo-Sig,Choi, Kyu-Myung,Kim, Hyun-Woo,Lee, Seung-Chul,Hwang, Seung-Ho The Institute of Electronics and Information Engin 2009 Journal of semiconductor technology and science Vol.9 No.4
Moore's law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-$\kappa$ metal gate, which cuts gate leakage current by a factor of 10 in 32 nm CMOS technology. A 45 nm mobile SoC is shown as the case study of the mixed use of low power methodologies.
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Introduction to Industrial Applications of Low Power Design Methodologies
Hyung-Ock Kim,Bong Hyun Lee,Jung Yon Choi,Hyo-Sig Won,Kyu-Myung Choi,Hyun Woo Kim,Seung Chul Lee,Seung Ho Hwang 대한전자공학회 2009 Journal of semiconductor technology and science Vol.9 No.4
Moore’s law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers’ main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-κ metal gate, which cuts gate leakage current by a factor of 10 in 32 ㎚ CMOS technology. A 45 ㎚ mobile SoC is shown as the case study of the mixed use of low power methodologies.
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Liu, Lianxi,Mu, Junchao,Yuan, Wenzhi,Tu, Wei,Zhu, Zhangming,Yang, Yintang The Korean Institute of Power Electronics 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.3
For wearable health monitoring systems, a fundamental problem is the limited space for storing energy, which can be translated into a short operational life. In this paper, a highly efficient active voltage doubling rectifier with a wide input range for micro-piezoelectric energy harvesting systems is proposed. To obtain a higher output voltage, the Dickson charge pump topology is chosen in this design. By replacing the passive diodes with unbalanced-biased comparator-controlled active counterparts, the proposed rectifier minimizes the voltage losses along the conduction path and solves the reverse leakage problem caused by conventional comparator-controlled active diodes. To improve the rectifier input voltage sensitivity and decrease the minimum operational input voltage, two low power common-gate comparators are introduced in the proposed design. To keep the comparator from oscillating, a positive feedback loop formed by the capacitor C is added to it. Based on the SMIC 0.18-μm standard CMOS process, the proposed rectifier is simulated and implemented. The area of the whole chip is 0.91×0.97 mm<sup>2</sup>, while the rectifier core occupies only 13% of this area. The measured results show that the proposed rectifier can operate properly with input amplitudes ranging from 0.2 to 1.0V and with frequencies ranging from 20 to 3000 Hz. The proposed rectifier can achieve a 92.5% power conversion efficiency (PCE) with input amplitudes equal to 0.6 V at 200 Hz. The voltage conversion efficiency (VCE) is around 93% for input amplitudes greater than 0.3 V and load resistances larger than 20kΩ.
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Lianxi Liu,Junchao Mu,Wenzhi Yuan,Wei Tu,Zhangming Zhu,Yintang Yang 전력전자학회 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.3
For wearable health monitoring systems, a fundamental problem is the limited space for storing energy, which can be translated into a short operational life. In this paper, a highly efficient active voltage doubling rectifier with a wide input range for micro-piezoelectric energy harvesting systems is proposed. To obtain a higher output voltage, the Dickson charge pump topology is chosen in this design. By replacing the passive diodes with unbalanced-biased comparator-controlled active counterparts, the proposed rectifier minimizes the voltage losses along the conduction path and solves the reverse leakage problem caused by conventional comparator-controlled active diodes. To improve the rectifier input voltage sensitivity and decrease the minimum operational input voltage, two low power common-gate comparators are introduced in the proposed design. To keep the comparator from oscillating, a positive feedback loop formed by the capacitor C is added to it. Based on the SMIC 0.18-μm standard CMOS process, the proposed rectifier is simulated and implemented. The area of the whole chip is 0.91×0.97 ㎟, while the rectifier core occupies only 13% of this area. The measured results show that the proposed rectifier can operate properly with input amplitudes ranging from 0.2 to 1.0V and with frequencies ranging from 20 to 3000 Hz. The proposed rectifier can achieve a 92.5% power conversion efficiency (PCE) with input amplitudes equal to 0.6 V at 200 Hz. The voltage conversion efficiency (VCE) is around 93% for input amplitudes greater than 0.3 V and load resistances larger than 20kΩ.
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