A Study on the Electrical Characteristics of Ultra Thin Gate Oxide

Gum-Yong Eom 한국전기전자재료학회 2004 Transactions on Electrical and Electronic Material Vol.5 No.5

Deep sub-micron device required to get the superior ultra thin gate oxide characteristics. In this research, I will recommend a novel shallow trench isolation structure(STI) for thin gate oxide and a N2O gate oxide 30 Å by NO ambient process. The local oxidation of silicon(LOCOS) isolation has been replaced by the shallow trench isolation which has less encroachment into the active device area. Also for N2O gate oxide 30 Å, ultra thin gate oxide 30 Å was formed by using the N2O gate oxide formation method on STI structure and LOCOS structure. For the metal electrode and junction, TiSi2 process was performed by RTP annealing at 850 ℃ for 29 sec. In the viewpoints of the physical characteristics of MOS capacitor, STI structure was confirmed by SEM. STI structure was expected to minimize the oxide loss at the channel edge. Also, STI structure is considered to decrease the threshold voltage, result in a lower Ti/TiN resistance(Ω/cont.) and higher capacitance-gate voltage(C-V) that made the STI structure more effective. In terms of the TDDB(sec) characteristics, the STI structure showed the stable value of 25 % ~ 90 % more than 55 sec. In brief, analysis of the ultra thin gate oxide 30 Å proved that STI isolation structure and salicidation process presented in this study. I could achieve improved electrical characteristics and reliability for deep submicron devices with 30 Å N2O gate oxide.

A Study on the Electrical Characteristics of Ultra Thin Gate Oxide

Eom, Gum-Yong The Korean Institute of Electrical and Electronic 2004 Transactions on Electrical and Electronic Material Vol.5 No.5

Deep sub-micron device required to get the superior ultra thin gate oxide characteristics. In this research, I will recommend a novel shallow trench isolation structure(STI) for thin gate oxide and a $N_2$O gate oxide 30 $\AA$ by NO ambient process. The local oxidation of silicon(LOCOS) isolation has been replaced by the shallow trench isolation which has less encroachment into the active device area. Also for $N_2$O gate oxide 30 $\AA$, ultra thin gate oxide 30 $\AA$ was formed by using the $N_2$O gate oxide formation method on STI structure and LOCOS structure. For the metal electrode and junction, TiSi$_2$ process was performed by RTP annealing at 850 $^{\circ}C$ for 29 sec. In the viewpoints of the physical characteristics of MOS capacitor, STI structure was confirmed by SEM. STI structure was expected to minimize the oxide loss at the channel edge. Also, STI structure is considered to decrease the threshold voltage, result in a lower Ti/TiN resistance( Ω /cont.) and higher capacitance-gate voltage(C- V) that made the STI structure more effective. In terms of the TDDB(sec) characteristics, the STI structure showed the stable value of 25 % ~ 90 % more than 55 sec. In brief, analysis of the ultra thin gate oxide 30 $\AA$ proved that STI isolation structure and salicidation process presented in this study. I could achieve improved electrical characteristics and reliability for deep submicron devices with 30 $\AA$ $N_2$O gate oxide.

Deuterium-incorporated Gate Oxide of MOS Devices Fabricated by Using Deuterium Ion Implantation

이재성,Kevin L. Lear 한국물리학회 2012 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.60 No.7

In the aspect of metal-oxide-semiconductor (MOS) device reliability, deuterium-incorporated gate oxide could be utilized to suppress the wear-out that is combined with oxide trap generation. An alternative deuterium process for the passivation of oxide traps or defects in the gate oxide of MOS devices has been suggested in this study. The deuterium ion is delivered to the location where the gate oxide resides by using an implantation process and subsequent N2 annealing process at the back-end of metallization process. A conventional MOS field-effect transistor (MOSFET) with a 3-nm-thick gate oxide and poly-to-ploy capacitor sandwiched with 20-nm-thick SiO2 were fabricated in order to demonstrate the deuterium effect in our process. An optimum condition of ion implantation was necessary to account for the topography of the overlaying layers in the device structure and to minimize the physical damage due to the energy of the implanted ion. Device parameter variations, the gate leakage current, and the dielectric breakdown phenomenon were investigated in the deuterium-ion-implanted devices. We found the isotope effect between hydrogen- and deuterium-implanted devices and an improved electrical reliability in the deuterated gate oxide. This implies that deuterium bonds are generated effectively at the Si/SiO2 interface and in the SiO2 bulk.

STI를 이용한 서브 0.1$\mu\textrm{m}$VLSI CMOS 소자에서의 초박막게이트산화막의 박막개선에 관한 연구

엄금용,오환술 한국전기전자재료학회 2000 전기전자재료학회논문지 Vol.13 No.9

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

가우스 함수의 파라미터에 따른 비대칭형 무접합 이중 게이트 MOSFET의 문턱전압 이하 스윙 분석

정학기 ( Hakkee Jung ) 한국전기전자재료학회 2022 전기전자재료학회논문지 Vol.35 No.3

The subthreshold swing (SS) of an asymmetric junctionless double gate (AJLDG) MOSFET is analyzed by the use of Gaussian function. In the asymmetric structure, the thickness of the top/bottom oxide film and the flat-band voltages of top gate (Vfbf) and bottom gate (Vfbb) could be made differently, so the change in the SS for these factors is analyzed with the projected range and standard projected deviation which are parameters for the Gaussian function. An analytical subthreshold swing model is presented from the Poisson’s equation, and it is shown that this model is in a good agreement with the numerical model. As a result, the SS changes linearly according to the geometric mean of the top and bottom oxide film thicknesses, and if the projected range is less than half of the silicon thickness, the SS decreases as the top gate oxide film is smaller. Conversely, if the projected range is bigger than a half of the silicon thickness, the SS decreases as the bottom gate oxide film is smaller. In addition, the SS decreases as Vfbb-Vfbf increases when the projected range is near the top gate, and the SS decreases as Vfbb-Vfbf decreases when the projected range is near the bottom gate. It is necessary that one should pay attention to the selection of the top/bottom oxide thickness and the gate metal in order to reduce the SS when designing an AJLDG MOSFET.

Impact of gate protection silicon nitride film on the sub-quarter micron transistor performances in dynamic random access memory devices

Choy, J.-H. The Korea Association of Crystal Growth 2004 韓國結晶成長學會誌 Vol.14 No.2

Gate protection $SiN_x$ as an alternative to a conventional re-oxidation process in Dynamic Random Access Memory devices is investigated. This process can not only protect the gate electrode tungsten against oxidation, but also save the thermal budget due to the re-oxidation. The protection $SiN_x$ process is applied to the poly-Si gate, and its device performance is measured and compared with the re-oxidation processed poly-Si gate. The results on the gate dielectric integrity show that etch damage-curing capability of protection $SiN_x$ is comparable to the re-oxidation process. In addition, the hot carrier immunity of the $SiN_x$ deposited gate is superior to that of re-oxidation processed gate.

중수소 이온 주입된 게이트 산화막을 갖는 MOSFET의 전기적 특성

이재성(Jae-Sung Lee) 大韓電子工學會 2010 電子工學會論文誌-SD (Semiconductor and devices) Vol.47 No.4

중수소 결합이 존재하는 게이트 산화막을 갖는 MOSFET는 일반 MOSFET에 비해 신뢰성이 개선된다고 알려져 있다. 본 연구에서는 MOS 소자의 게이트 산화막내에 중수소를 분포시키기 위해 새로운 중수소 이온 주입법을 제안하였다. MOS 소자를 구성하는 층간 물질 및 중수소가 분포할 위치에 따라 중수소 이온 주입 에너지는 다양하게 변하게 된다. 이온 주입 후 발생할 수 있는 물질적 손상을 방지하기 위해 후속 열처리 공정이 수반된다. 제조된 일반 MOSFET를 사용하여 제안된 중수소이온 주입을 통해 게이트 산화막내 계면 및 bulk 결함이 감소함을 확인하였다. 그러나 이온 주입으로 인해 실리콘 기판의 불순물 농도가 변화할 수 있으므로 이온 주입 조건의 최적화가 필요하다. 중수소 이온 주입된 MOSFET의 CV 및 IV 특성 조사를 통해 이온 주입으로 인한 트랜지스터의 성능 변화는 발생하지 않았다. MOSFET with deuterium-incorporated gate oxide shows enhanced reliability compared to conventional MOSFET. We present an alternative process whereby deuterium is delivered to the location where the gate oxide reside by an implantation process. Deuterium ions were implanted using two different energies to account for the topography of the overlaying layers and placing the D peak at the top of gate oxide. A short anneal at forming gas was performed to remove the D-implantation damage. We have observed that deuterium ion implantation into the gate oxide region can successfully remove the interface states and the bulk defects. But the energy and the dose of the deuterium implant need to be optimized to maintain the Si substrates dopant activation, while generating deuterium bonds inside gate oxide. CV and IV characteristics studies also determined that the deuterium implant dose not degrade the transistor performance.

고압 중수소 열처리 효과에 의해 조사된 수소 결합 관련 박막 게이트 산화막의 열화

이재성 대한전자공학회 2004 電子工學會論文誌-SD (Semiconductor and devices) Vol.41 No.11

두께가 약 3 nm 인 게이트 산화막을 갖는 P 및 NMOSFET를 제조하여 높은 압력 (5 atm.)의 중수소 및 수소 분위기에서 후속 열처리를 각각 행하여 중수소 효과(동위원소 효과)를 관찰하였다. 소자에 대한 스트레스는 -2.5V ≤ V/sub g/ ≤-4.0V 범위에서 100℃의 온도를 유지하며 진행되었다. 낮은 스트레스 전압에서는 실리콘 계면에 존재하는 정공에 의하여 게이트 산화막의 열화가 진행되었다. 그러나 스트레스 전압을 증가시킴으로써 높은 에너지를 갖는 전자에 의한 계면 결함 생성이 열화의 직접적인 원인이 됨을 알 수 있었다. 본 실험조건에서는 실리콘 계면에서 phonon 산란이 많이 발생하여 impact ionization에 의한 "hot" 정공의 생성은 무시할 수 있었다. 중수소 열처리를 행함으로써 수소 열처리에 비해 소자의 파라미터 변화가 적었으며, 게이트 산화막의 누설전류도 억제됨이 확인되었다. 이러한 결과로부터 impact ionization이 발생되지 않을 정도의 낮은 스트레스 전압동안 발생하는 게이트 산화막내 결함 생성은 수소 결합과 직접적인 관계가 있음을 확인하였다. Experimental results are presented for the degradation of 3 nm-thick gate oxide under -2.5V $\leq$ V$_{g}$ $\leq$-4.0V stress and 10$0^{\circ}C$ conditions using P and NMOSFETs that are annealed with hydrogen or deuterium gas at high-pressure (5 atm). The degradation mechanisms are highly dependent on stress conditions. For low gate voltage, hole-trapping is found to dominate the reliability of gate oxide both in P and NMOSFETs. With increasing gate voltage to V$_{g}$ =-4.0V, the degradation becomes dominated by electron-trapping in NMOSFETs, however, the generation rate of "hot" hole was very low, because most of tunneling electrons experienced the phonon scattering before impact ionization at the Si interface. Statistical parameter variations as well as the gate leakage current depend on and are improved by high-pressure deuterium annealing, compared to corresponding hydrogen annealing. We therefore suggest that deuterium is effective in suppressing the generation of traps within the gate oxide. Our results therefore prove that hydrogen related processes are at the origin of the investigated oxide degradation.gradation.

Nitrided oxide에 의한 Boron penetration 방지 효과 연구

송오성 서울시립대학교 산업기술연구소 1998 산업기술연구소논문집 Vol.6 No.1

We need to speed up the logic devices by reducing the gate oxide thickness. Boron penetration, boron atoms diffuse into the silicon substrate during dual gate process, may deteriorate the CMOS logic devices. We investigate the microstructures and the degree of the boron penetration of both 4 nm-thick pure oxide and 4nm-thick nitrided oxide (SiON) with tranmission electron microscope (TEM) and secondary ion mass spectroscopy(SIMS) depth profiling, respectively Boron penetrated through pure oxide layers easily, but never diffuse through SiON layers. We confirmed the amount of the penetrated B concentration through pure SiO2 was 1019 B atoms/cm3, while for SiON was below 1016 B atoms/cm3. The solubility of [N] in SiON was 8 at% in SiO2, layers. We suggest that employing SiON as a gate oxide for high speed logic devices with gate oxide thickness below 4 nm is favorable.

MOSFET 게이트 산화막내 결함 생성 억제를 위한 효과적인 중수소 이온 주입

이재성(Jae-Sung Lee),도승우(Seung-Woo Do),이용현(Yong-Hyun Lee) 대한전자공학회 2008 電子工學會論文誌-SD (Semiconductor and devices) Vol.45 No.7

중수소 처리된 3 ㎚ 두께의 게이트 산화막을 갖는 MOSFET를 제조하여 정전압 스트레스 동안의 게이트 산화막의 열화를 조사하였다. 중수소 처리는 열처리와 이온 주입법을 사용하여 각각 이루어졌다. 열처리 공정을 통해서는 게이트 산화막내 중수소의 농도를 조절하기가 힘들었다. 게이트 산화막내에 존재하는 과잉 중수소 결합은 열화를 가속시키기 때문에, 열처리 공정을 행한 소자에서 신뢰성이 표준공정에 의한 소자에 비해 저하되고 있음을 확인하였다. 그러나 중수소 이온 주입 방법을 통해서는 소자의 신뢰성이 개선됨을 확인하였다. 스트레스에 의한 게이트 누설 전류 변화 및 구동 특성 변화는 게이트 산화막내의 중수소 농도와 관련이 있으며, 이러한 특성은 적절한 공정 조건을 갖는 이온 주입법을 통해 개선할 수 있었다. 특히, 큰 스트레스 전압의 PMOSFET에서 중수소의 효과가 뚜렷하게 나타났으며, 이는 “hot” 정공과 중수소의 반응과 관련이 있는 것으로 판단된다. Experiment results are presented for gate oxide degradation under the constant voltage stress conditions using MOSFETs with 3-㎚-thick gate oxides that are treated by deuterium gas. Two kinds of methods, annealing and implantation, are suggested for the effective deuterium incorporation. Annealing process was rather difficult to control the concentration of deuterium. Because the excess deuterium in gate oxide could be a precursor for the wear-out of gate oxide film, we found annealing process did not show improved characteristics in device reliability, compared to conventional process. However, deuterium implantation at the back-end process was effective method for the deuterated gate oxide. Device parameter variations as well as the gate leakage current depend on the deuterium concentration and are improved by low-energy deuterium implantation, compared to those of conventional process. Especially, we found that PMOSFET experienced the high voltage stress shows a giant isotope effect. This is likely because the reaction between “hot” hole and deuterium is involved in the generation of oxide trap.