실리콘 웨이퍼 연마헤드의 강제구동 방식이 웨이퍼 연마 평탄도에 미치는 영향 연구

김경진,박중윤 한국반도체디스플레이기술학회 2014 반도체디스플레이기술학회지 Vol.13 No.1

Since the semiconductor manufacturing requires the silicon wafers with extraordinary degree of surface flatness, the surface polishing of wafers from ingot cutting is an important process for deciding surface quality of wafers. The present study introduces the development of wafer polishing equipment and, especially, the wafer polishing head that employs the forced self-driving of installed silicon wafer as well as the wax wafer mounting technique. A series of wafer polishing tests have been carried out to investigate the effects of self-driving function in wafer polishing head. The test results for wafer planarization showed that the LLS counts and SBIR of polished wafer surfaces were generally improved by adopting the self-driven polishing head in wafer polishing stations.

Automated Wafer Separation from the Stacked Array of Solar Cell Silicon Wafers Using Continuous Water Jet

곽호상,김경진,김동주 한국반도체디스플레이기술학회 2010 반도체디스플레이기술학회지 Vol.9 No.2

In response to the industrial needs for automated handling of very thin solar cell wafers, this paper presents the design concept for the individual wafer separation from the stacked wafers by utilizing continuous water jet. The experimental apparatus for automated wafer separation was constructed and it includes the water jet system and the microprocessor controlled wafer stack advancing system. Through a series of tests, the performance of the proposed design is quantified into the success rate of single wafer separation and the rapidity of processing wafer stack. Also, the inclination angle of wafer equipped cartridge and the water jet flowrate are found to be important parameters to be considered for process optimization. The proposed design shows the concept for fast and efficient processing of wafer separation and can be implemented in the automated manufacturing of silicon based solar cell wafers.

Polished Wafer와 Epi-Layer Wafer의 표면 처리에 따른 표면 화학적/물리적 특성

김진서,서형탁,Kim, Jin-Seo,Seo, Hyungtak 한국재료학회 2014 한국재료학회지 Vol.24 No.12

Physical and chemical changes in a polished wafer and in $2.5{\mu}m$ & $4{\mu}m$ epitaxially grown Si layer wafers (Epilayer wafer) after surface treatment were investigated. We characterized the influence of surface treatment on wafer properties such as surface roughness and the chemical composition and bonds. After each surface treatment, the physical change of the wafer surface was evaluated by atomic force microscopy to confirm the surface morphology and roughness. In addition, chemical changes in the wafer surface were studied by X-ray photoemission spectroscopy measurement. Changes in the chemical composition were confirmed before and after the surface treatment. By combined analysis of the physical and chemical changes, we found that diluted hydrofluoric acid treatment is more effective than buffered oxide etching for $SiO_2$ removal in both polished and Epi-Layer wafers; however, the etch rate and the surface roughness in the given treatment are different among the polished $2.5{\mu}m$ and $4{\mu}m$ Epi-layer wafers in spite of the identical bulk structural properties of these wafers. This study therefore suggests that independent surface treatment optimization is required for each wafer type, $2.5{\mu}m$ and $4{\mu}m$, due to the meaningful differences in the initial surface chemical and physical properties.

저유전체 고분자 접착 물질을 이용한 웨이퍼 본딩을 포함하는 웨이퍼 레벨 3차원 집적회로 구현에 관한 연구

Kwon, Yongchai,Seok, Jongwon,Lu, Jian-Qiang,Cale, Timothy,Gutmann, Ronald 한국화학공학회 2007 Korean Chemical Engineering Research(HWAHAK KONGHA Vol. No.

웨이퍼 레벨(WL) 3차원(3D) 집적을 구현하기 위해 저유전체 고분자를 본딩 접착제로 이용한 웨이퍼 본딩과, 적층된 웨이퍼간 전기배선 형성을 위해 구리 다마신(damascene) 공정을 사용하는 방법을 소개한다. 이러한 방법을 이용하여 웨이퍼 레벨 3차원 칩의 특성 평가를 위해 적층된 웨이퍼간 3차원 비아(via) 고리 구조를 제작하고, 그 구조의 기계적, 전기적 특성을 연속적으로 연결된 서로 다른 크기의 비아를 통해 평가하였다. 또한, 웨이퍼간 적층을 위해 필수적인 저유전체 고분자 수지를 이용한 웨이퍼 본딩 공정의 다음과 같은 특성 평가를 수행하였다. (1) 광학 검사에 의한 본딩된 영역의 정도 평가, (2) 면도날(razor blade) 시험에 의한 본딩된 웨이퍼들의 정성적인 본딩 결합력 평가, (3) 4-점 굽힘시험(four point bending test)에 의한 본딩된 웨이퍼들의 정량적인 본딩 결합력 평가. 본 연구를 위해 4가지의 서로 다른 저유전체 고분자인 benzocyclobutene(BCB), Flare, methylsilsesquioxane(MSSQ) 그리고 parylene-N을 선정하여 웨이퍼 본딩용 수지에 대한 적합성을 검토하였고, 상기 평가 과정을 거쳐 BCB와 Flare를 1차적인 본딩용 수지로 선정하였다. 한편 BCB와 Flare를 비교해 본 결과, Flare를 이용하여 본딩된 웨이퍼들이 BCB를 이용하여 본딩된 웨이퍼보다 더 높은 본딩 결합력을 보여주지만, BCB를 이용해 본딩된 웨이퍼들은 여전히 칩 back-end-of-the-line (BEOL) 공정조건에 부합되는 본딩 결합력을 가지는 동시에 동공이 거의 없는 100%에 가까운 본딩 영역을 재현성있게 보여주기 때문에 본 연구에서는 BCB가 본딩용 수지로 더 적합하다고 판단하였다. A technology platform for wafer-level three-dimensional integration circuits (3D-ICs) is presented, and that uses wafer bonding with low-k polymeric adhesives and Cu damascene inter-wafer interconnects. In this work, one of such technical platforms is explained and characterized using a test vehicle of inter-wafer 3D via-chain structures. Electrical and mechanical characterizations of the structure are performed using continuously connected 3D via-chains. Evaluation results of the wafer bonding, which is a necessary process for stacking the wafers and uses low-k dielectrics as polymeric adhesive, are also presented through the wafer bonding between a glass wafer and a silicon wafer. After wafer bonding, three evaluations are conducted; (1) the fraction of bonded area is measured through the optical inspection, (2) the qualitative bond strength test to inspect the separation of the bonded wafers is taken by a razor blade, and (3) the quantitative bond strength is measured by a four point bending. To date, benzocyclobutene (BCB), $Flare^{TM}$, methylsilsesquioxane (MSSQ) and parylene-N were considered as bonding adhesives. Of the candidates, BCB and $Flare^{TM}$ were determined as adhesives after screening tests. By comparing BCB and $Flare^{TM}$, it was deduced that BCB is better as a baseline adhesive. It was because although wafer pairs bonded using $Flare^{TM}$ has a higher bond strength than those using BCB, wafer pairs bonded using BCB is still higher than that at the interface between Cu and porous low-k interlevel dielectrics (ILD), indicating almost 100% of bonded area routinely.

Automated Wafer Separation from the Stacked Array of Solar Cell Silicon Wafers Using Continuous Water Jet

Kim, Kyoung-Jin,Kim, Dong-Joo,Kwak, Ho-Sang The Korean Society Of SemiconductorDisplay Technol 2010 반도체디스플레이기술학회지 Vol.9 No.2

In response to the industrial needs for automated handling of very thin solar cell wafers, this paper presents the design concept for the individual wafer separation from the stacked wafers by utilizing continuous water jet. The experimental apparatus for automated wafer separation was constructed and it includes the water jet system and the microprocessor controlled wafer stack advancing system. Through a series of tests, the performance of the proposed design is quantified into the success rate of single wafer separation and the rapidity of processing wafer stack. Also, the inclination angle of wafer equipped cartridge and the water jet flowrate are found to be important parameters to be considered for process optimization. The proposed design shows the concept for fast and efficient processing of wafer separation and can be implemented in the automated manufacturing of silicon based solar cell wafers.

Evaluation of a Wafer Transportation Speed for Propulsion Nozzle Array on Air Levitation System

In-Ho Moon,Young-Kyu Hwang 대한기계학회 2006 JOURNAL OF MECHANICAL SCIENCE AND TECHNOLOGY Vol.20 No.9

A transportation system of single wafer has been developed to be applied to semiconductor manufacturing process of the next generation. In this study, the experimental apparatus consists of two kinds of track, one is for propelling a wafer, so called control track, the other is for generating an air film to transfer a wafer, so called transfer track. The wafer transportation speed has been evaluated by the numerical and the experimental methods for three types of nozzle position array (i.e., the front-, face- and rear-array) in an air levitation system. Test facility for 300 mm wafer has been equipped with two control tracks and one transfer track of 1500 mm length from the starting point to the stopping point. From the present results, it is found that the experimental values of the wafer transportation speed are well in agreement with the computed ones. Namely, the computed values of the maximum wafer transportation speed Vmax are slightly higher than the experimental ones by about 15~20%. The disparities in Vmax between the numerical and the experimental results become smaller as the air velocity increases. Also, at the same air flow rate, the order of wafer transportation speeds is: Vmax for the front-array > Vmax for the face-array >Vmax for the rear-array. However, the face-array is rather more stable than any other type of nozzle array to ensure safe transportation of a wafer.

최적조건 선정을 위한 Pad 특성과 Wafer Final Polishing의 가공표면에 관한 연구

원종구(Jong-Koo Won),이은상(Eun-Sang Lee),이상균(Sang-Gyun Lee) 한국기계가공학회 2012 한국기계가공학회지 Vol.11 No.1

Polishing is one of the important methods in manufacturing of Si wafers and in thinning of completed device wafers. This study will report the characteristic of wafer according to processing time, machining speed and pressure which have major influence on the abrasion of Si wafer polishing. It is possible to evaluation of wafer abrasion by load cell and infrared temperature sensor. The characteristic of wafer surface according to processing condition is selected to use a result data that measure a pressure, machining speed, and the processing time. This result is appeared by the characteristic of wafer surface in machining condition. Through that, the study cans evaluation a wafer characteristic in variable machining condition. It is important to obtain optimal condition. Thus the optimum condition selection of ultra precision Si wafer polishing using load cell and infrared temperature sensor. To evaluate each machining factor, use a data through each sensor. That evaluation of abrasion according to variety condition is selected to use a result data that measure a pressure, machining speed, and the processing time. And optimum condition is selected by this result.

박판 웨이퍼의 적재 시 손상 최소화 기술

이종항(Jong Hang Lee) 한국산학기술학회 2021 한국산학기술학회논문지 Vol.22 No.1

본 연구는 웨이퍼를 적재할 때 웨이퍼의 손상을 최소화 시키기 위한 기술이다. 반도체와 솔라셀에 이용되는 두께가 얇은 웨이퍼는 적재된 웨이퍼 사이의 표면 장력에 의해 웨이퍼의 분리를 어렵게 만들어 웨이퍼의 표면에 손상을 줄 수 있다. 이러한 웨이퍼의 손상을 최소화시키는 기술은 압축 공기를 웨이퍼 쪽으로 분사하고, 미소의 수평 이동 기구를 동시에 적용하는 것이다. 연구에 사용된 주요 실험 인자는 웨이퍼의 공급 속도, 압축 공기의 노즐 압력, 그리고 흡착헤드의 흡착 시간이다. 실험 결과, 동일한 노즐 압력에서 웨이퍼의 공급 속도가 빠를수록 파손율이 증가하고, 동일한 공급 속도에서는 노즐 압력이 낮을수록 파손율이 증가한다. 그리고, 웨이퍼를 흡착시키데 필요한 시간은 어느 수준 이상이면 웨이퍼의 공급 속도에 따른 파손율에는 큰 영향을 미치지 않는다. 본 연구의 실험 범위 안에서 최적의 실험 조건은 웨이퍼의 공급 속도 600 ea/hr, 압축 공기의 노즐 압력 0.55 MPa, 흡착 헤드의 흡착 시간 0.9 sec 이다. 또한, 반복성능 실험을 통해 개선된 기술은 웨이퍼의 파손율을 최소화시킬 수 있음을 보여 주었다. This paper presents a technique to minimize damaged wafers during loading. A thin wafer used in solar cells and semiconductors can be damaged easily. This makes it difficult to separate the wafer due to surface tension between the loaded wafers. A technique for minimizing damaged wafers is to supply compressed air to the wafer and simultaneously apply a small horizontal movement mechanism. The main experimental factors used in this study were the supply speed of wafers, the nozzle pressure of the compressed air, and the suction time of a vacuum head. A higher supply speed of the wafer under the same nozzle pressure and lower nozzle pressure under the same supply speed resulted in a higher failure rate. Furthermore, the damage rate, according to the wafer supply speed, was unaffected by the suction time to grip a wafer. The optimal experiment conditions within the experimental range of this study are the wafer supply speed of 600 ea/hr, nozzle air pressure of 0.55 MPa, and suction time of 0.9 sec at the vacuum head. In addition, the technology improved by the repeatability performance tests can minimize the damaged wafer rate.

실리콘 웨이퍼 연삭의 평탄도 특성 평가

김상철(Sangchul Kim),이상직(Sangjik Lee),정해도(Haedo Jeong),이석우(Seokwoo Lee),최헌종(Honzong Choi) 대한기계학회 2003 대한기계학회 춘추학술대회 Vol.2003 No.11

Ultra precision grinding technology has been developed from the refinement of the abrasive, the development of high stiffuess equipment and grinding skill. The conventional wafering process which consists of lapping, etching, 1st, 2nd and 3rd polishing has been changed to the new process which consists of precision surface grinding, final polishing and post cleaning. Especially, the ultra precision grinding of wafer improves the flatness of wafer and the efficiency of production. Furthermore, it has been not only used in bare wafer grinding, but also applied to wafer back grinding and SOI wafer grinding. This paper focuses on the flatness of the ground wafer. Generally, the ground wafer has concave profile because of the difference of wheel path density, grinding temperature and elastic deformation of the equipment. Wafer tilting is applied to avoid non-uniform material removal. Through the geometric analysis of wafer grinding process, the profile of the ground wafer is predicted by the development of profile simulator.

최적 dechucking 시스템 구현에 관한 연구

서종완,서희석,신명철,Seo, Jong-Wan,Suh, Hee-Seok,Shin, Myong-Chul 한국조명전기설비학회 2007 조명·전기설비학회논문지 Vol.21 No.5

반도체 공정에서 각 단계별 과정을 거친 후 dechucking시 wafer가 ESC(Electrostatic Chuck)로부터 방전되지 못하고, 잔류되어 있는 극성을 띤 전하(Electric charge)들에 의해 wafer와 ESC사이에 인력이 발생하여 wafer의 sliding, popping 및 wafer broken 등의 문제가 발생한다. 본 논문에서는 wafer와 ESC의 구성을 capacitor를 이용하여 modeling하고, PSpice를 사용하여 chucking system에 의한 wafer의 대전 현상을 모의하고 그 결과를 바탕으로 잔류전하를 방전시키기 위한 여러 가지 방법을 검토하여 최적의 잔류전하 제거 기법을 제시한다. 즉 별도의 전압원을 사용하여 (+)와 (-)를 교번하는 구형파를 인가함과 아울러 일정시간 동안 Plasma내에서 스위칭시킴으로써 ESC나 wafer에 charge되어 있는 극성을 띤 전하들을 중화(Neutralize) 시키도록 하였다. 그리고 이를 실제 하드웨어로 구현하여 실 공정에 적용한 결과를 제시한다. After the semiconductor processing, wafer is attracted by ESC(Electrostatic Chuck) with remaining electric charge. That causes too many problems for examples, sliding of wafer, popping or broken. This paper presents the model of ESC for silicon wafer, which is modeled by electrical circuit component such as capacitor. The simulations using PSpice result in the phenomenon of silicon wafer was charged by ESC. In this paper we suggest the discharging method. for wafer.