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Yun Seop Yu,B. H. Choi,안도열,S. H. Hong,S. H. Kim,황성우 한국물리학회 2004 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.44 No.1
We introduce a SPICE-compatible model for a oating-dot single-electron memory (FDSEM), which includes both the single-electron box (SEB) model and the modified SOI MOSFET model. In this model, a surface potential model for SOI devices is developed. The accuracy of the developed model is verified with experimental data from FDSEM devices.
Compact Capacitance Model of L-Shape Tunnel Field-Effect Transistors for Circuit Simulation
Yu, Yun Seop,Najam, Faraz The Korea Institute of Information and Commucation 2021 Journal of information and communication convergen Vol.19 No.4
Although the compact capacitance model of point tunneling types of tunneling field-effect transistors (TFET) has been proposed, those of line tunneling types of TFETs have not been reported. In this study, a compact capacitance model of an L-shaped TFET (LTFET), a line tunneling type of TFET, is proposed using the previously developed surface potentials and current models of P- and L-type LTFETs. The Verilog-A LTFET model for simulation program with integrated circuit emphasis (SPICE) was also developed to verify the validation of the compact LTFET model including the capacitance model. The SPICE simulation results using the Verilog-A LTFET were compared to those obtained using a technology computer-aided-design (TCAD) device simulator. The current-voltage characteristics and capacitance-voltage characteristics of N and P-LTFETs were consistent for all operational bias. The voltage transfer characteristics and transient response of the inverter circuit comprising N and P-LTFETs in series were verified with the TCAD mixed-mode simulation results.
Compact Current Model of Single-Gate/Double-Gate Tunneling Field-Effect Transistors
Yun Seop Yu,Faraz Najam 대한전기학회 2017 Journal of Electrical Engineering & Technology Vol.12 No.5
A compact current model applicable to both single-gate (SG) and double-gate (DG) tunneling field-effect transistors (TFETs) is presented. The model is based on Kane’s band-to-band tunneling (BTBT) model. In this model, the well-known and previously-reported quasi-2-D solution of Poisson’s equation is used for the surface potential and length of the tunneling path in the tunneling region. An analytical tunneling current expression is derived from expressions of derivatives of local electric field and surface potential with respect to tunneling direction. The previously reported correction factor with three fitting parameters, compensating for superlinear onset and saturation current with drain voltage, is used. Simulation results of the proposed TFET model are compared with those from a technology computer-aided-design (TCAD) simulator, and good agreement in all operational bias is demonstrated. The proposed SG/DG-TFET model is developed with Verilog-A for circuit simulation. A TFET inverter is simulated with the Verilog-A SG/DG-TFET model in the circuit simulator; the model exhibits typical inverter characteristics, thereby confirming its effectiveness.
A Multi-Gate Single-Electron Transistor Model for Circuit Simulations by SPICE
YUN SEOP YU 한국물리학회 2007 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.50 No.3
A new compact multi-gate single-electron transistor (MGSET) model for circuit simulations by SPICE is introduced. In addition to the multi-input gates, a random background charge QO is included in the model. The developed model is based on a linearized equivalent circuit and is implemented to the SmartSpice made by Silvaco. The drain-source current (Ids) versus gate-source voltage (Vgs) characteristics and the Ids versus drain-source voltage (Vds) characteristics, calculated by using the model, reproduce those of a Monte-Carlo simulator within a 1 % error. One simulation of SE-FET hybrid circuits, consisting of one MGSET and two MOSFETs, was successfully done.
Device Coupling Effects of Monolithic 3D Inverters
Yu, Yun Seop,Lim, Sung Kyu The Korea Institute of Information and Commucation 2016 Journal of information and communication convergen Vol.14 No.1
The device coupling between the stacked top/bottom field-effect transistors (FETs) in two types of monolithic 3D inverter (M3INV) with/without a metal layer in the bottom tier is investigated, and then the regime of the thickness T<sub>ILD</sub> and dielectric constant ε<sub>r</sub> of the inter-layer distance (ILD), the doping concentration N<sub>d</sub> (N<sub>a</sub>), and length L<sub>g</sub> of the channel, and the side-wall length L<sub>SW</sub> where the stacked FETs are coupled are studied. When N<sub>d</sub> (N<sub>a</sub>) < 10<sup>16</sup> cm<sup>-3</sup> and L<sub>SW</sub> < 20 nm, the threshold voltage shift of the top FET varies almost constantly by the gate voltage of the bottom FET, but when N<sub>d</sub> (N<sub>a</sub>) > 10<sup>16</sup> cm<sup>-3</sup> or L<sub>SW</sub> > 20 nm, the shift decreases and increases, respectively. M3INVs with T<sub>ILD</sub> ≥ 50 nm and ε<sub>r</sub> ≤ 3.9 can neglect the interaction between the stacked FETs, but when T<sub>ILD</sub> or ε<sub>r</sub> do not meet the above conditions, the interaction must be taken into consideration.
Comparison of Fall Detection Systems Based on YOLOPose and Long Short-Term Memory
Yun Seop Yu,Nam Ho Kim,Seung Su Jeong 한국정보통신학회 2024 Journal of information and communication convergen Vol.22 No.2
In this study, four types of fall detection systems – designed with YOLOPose, principal component analysis (PCA), convolutionalneural network (CNN), and long short-term memory (LSTM) architectures – were developed and compared in the detection ofeveryday falls. The experimental dataset encompassed seven types of activities: walking, lying, jumping, jumping in activities ofdaily living, falling backward, falling forward, and falling sideways. Keypoints extracted from YOLOPose were entered into thefollowing architectures: RAW-LSTM, PCA-LSTM, RAW-PCA-LSTM, and PCA-CNN-LSTM. For the PCA architectures, thereduced input size stemming from a dimensionality reduction enhanced the operational efficiency in terms of computational timeand memory at the cost of decreased accuracy. In contrast, the addition of a CNN resulted in higher complexity and loweraccuracy. The RAW-LSTM architecture, which did not include either PCA or CNN, had the least number of parameters, whichresulted in the best computational time and memory while also achieving the highest accuracy.
Yun Seop Yu 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.4
A full-range analytic drain current model for depletion-mode long-channel surrounding-gate nanowire field-effect transistor (SGNWFET) is proposed. The model is derived from the solution of the 1-D cylindrical Poisson equation which includes dopant and mobile charges, by using the Pao-S모 gradual channel approximation and the full-depletion approximation. The proposed model captures the phenomenon of the bulk conduction mechanism in all regions of device operation (subthreshold, linear, and saturation regions). It has been shown that the continuous model is in complete agreement with the numerical simulations.
Yu, Yun-Seop The Institute of Electronics and Information Engin 2010 Journal of semiconductor technology and science Vol.10 No.2
We propose a semi-analytical current conduction model for depletion-mode n-type nanowire field-effect transistors (NWFETs) with top-gate structure. The NWFET model is based on an equivalent circuit consisting of two back-to-back Schottky diodes for the metal-semiconductor (MS) contacts and the intrinsic top-gate NWFET. The intrinsic top-gate NWFET model is derived from the current conduction mechanisms due to bulk charges through the center neutral region as well as of accumulation charges through the surface accumulation region, based on the electrostatic method, and thus it includes all current conduction mechanisms of the NWFET operating at various top-gate bias conditions. Our previously developed Schottky diode model is used for the MS contacts. The newly developed model is integrated into ADS, in which the intrinsic part of the NWFET is developed by utilizing the Symbolically Defined Device (SDD) for an equation-based nonlinear model. The results simulated from the newly developed NWFET model reproduce considerably well the reported experimental results.