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Novel Current Driving Circuit for Active Matrix Organic Light Emitting Diode
Yil Suk Yang,이대우,노태문,Woo H. Kwon,Jongdae Kim 한국전자통신연구원 2004 ETRI Journal Vol.26 No.5
ABSTRACTThis paper describes a novel current driving circuit for an active matrix organic light emitting diode (AMOLED). The proposed current driving circuit has a lower power consumption and higher chip density for the AMOLED display compared with the conventional one because all elements operate at a normal voltage and are shielded from the high voltage of the panel. The chip size and power consumption of the current driving circuit for an AMOLED can be improved by about 30 to 40% and 10 to 20%, respectively, compared with the conventional one.
Yang, Yil-Suk,Roh, Tae-Moon,Yeo, Soon-Il,Kwon, Woo-H.,Kim, Jong-Dae The Institute of Electronics and Information Engin 2009 Journal of semiconductor technology and science Vol.9 No.1
This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.
Power-aware 32Bit SIMSD Path Architecture Using Single/Parallel Mode Bit and 2 Step Gating Technique
Yil Suk Yang,Tae Moom Roh,Dae Woo Lee,Nae Soo Cho,Woo H. Kwon,Jongdae Kim 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
This paper describes 32bit parallel data path architecture for high-energy efficiency. We apply a parallel architecture, a 2 step gating technique and single/parallel mode bit in order to high energy efficiency. The energy efficiency of the proposed 32bit SIMSD (Single Instruction Multiple/Single Data) path architecture can improve about 20% than that of the conventional 32bit parallel data architecture without using 2 step gating technique.
Yil Suk Yang,Woo H. Kwon,Tae Moon Roh,Soon il Yeo,Jongdae Kim 대한전자공학회 2009 Journal of semiconductor technology and science Vol.8 No.1
Abstract—This paper describes design of high energy efficiency 32 bit parallel processor core using instructtion- levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.
Yil Suk Yang,Tae Moon Roh,Soon il Yeo,Woo H. Kwon,Jongdae Kim 대한전자공학회 2009 Journal of semiconductor technology and science Vol.9 No.1
This paper describes design of high energy efficiency 32 bit parallel processor core using instructtion-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.