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Yang, Younghwi,Jeong, Hanwool,Song, Seung Chul,Wang, Joseph,Yeap, Geoffrey,Jung, Seong-Ook IEEE 2016 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.63 No.7
<P>Although near-threshold voltage (NTV) operation is an attractive means of achieving high energy efficiency, it can degrade the circuit stability of static random access memory (SRAM) cells. This paper proposes an NTV 7T SRAM cell in a 14 nm FinFET technology to eliminate read disturbance by disconnecting the path from the bit-line to the cross-coupled inverter pair using the transmission gate. In the proposed 7T SRAM cell, the half-select issue is resolved, meaning that no write-back operation is required. A folded-column structure is applied to the proposed 7T SRAM cell to reduce the read access time and energy consumption. To reduce the standby power, the proposed 7T SRAM cell uses only a single bit-line for both read and write operations. To achieve proper '1' writing operation with a single bit-line, a two-phase approach is proposed. Compared to the conventional 8T SRAM cell, the proposed 7T SRAM cell improves the read access time, energy, and standby power by 13%, 42%, and 23%, respectively, with a 3% smaller cell area.</P>
Younghwi Yang,Juhyun Park,Seung Chul Song,Wang, Joseph,Yeap, Geoffrey,Seong-Ook Jung IEEE 2015 IEEE transactions on very large scale integration Vol.23 No.11
<P>Although near-threshold (Vth) operation is an attractive method for energy and performance-constrained applications, it suffers from problems in terms of circuit stability, particularly, for static random access memory (SRAM) cells. This brief proposes a near-Vth 9T SRAM cell implemented in a 22-nm FinFET technology. The read buffer of the proposed cell ensures read stability by decoupling the stored node from the read bit-line and improves read performance using a one-transistor read path. Energy and standby power are reduced by eliminating the sub-Vth leakage current in the read buffer. For accurate sensing yield estimation, a new yield-estimation method is also proposed, which considers the dynamic trip voltage. The proposed SRAM cell can achieve a minimum operating voltage of 0.3 V.</P>
Younghwi Yang,Juhyun Park,Seung Chul Song,Wang, Joseph,Yeap, Geoffrey,Seong-Ook Jung IEEE 2015 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.62 No.6
<P>As the semiconductor technology scales down, the read stability and write ability of a static random-access memory (SRAM) cell are degraded because of the increased mismatch among its transistors. Extremely thin silicon-on-insulator is one of the attractive candidates to reduce this mismatch, and it offers an independent back-gate control using a thin buried oxide. The implementation of back-gate control has recently attracted much interest to improve the read stability and write ability. In this paper, we propose a selective cell current (ICELL) boosting scheme (SIB) and an asymmetric back-gate control write-assist (ABC-WA) circuit. SIB enhances the read performance by selectively boosting ICELL of the SRAM cells. ABC-WA enhances the write ability by forward biasing the NMOSs at one side, which improves the write ability with reduction in the dynamic power overhead and without requiring a voltage generator. The proposed SRAM design improves the read performance and energy by 38.6% and 24.9%, respectively.</P>
Design of a 22-nm FinFET-Based SRAM With Read Buffer for Near-Threshold Voltage Operation
Juhyun Park,Younghwi Yang,Hanwool Jeong,Seung Chul Song,Wang, Joseph,Yeap, Geoffrey,Seong-Ook Jung Institute of Electrical and Electronics Engineers 2015 IEEE transactions on electron devices Vol. No.
<P>A near-threshold voltage (V<SUB>th</SUB>) operation circuit is important for both energy- and performance-constrained applications. The conventional 6-T SRAM bit-cell designed for super-V<SUB>th</SUB> operation cannot achieve the target SRAM bit-cell margins such as the hold stability, read stability, and write ability margins in the near-V<SUB>th</SUB> region. The recently proposed SRAM bit-cells with read buffer suffer from the problems of low read 0 sensing margin and large read 1 sensing time in the near-V<SUB>th</SUB> region. This paper proposes a read buffer with adjusted the number of fins or V<SUB>th</SUB> to resolve the problems in the near-V<SUB>th</SUB> region. This paper also proposes a design method for pull-up, pull-down, and pass-gate transistors to achieve the target hold stability and presents an effective write assist circuit to achieve the target write ability in the near-V<SUB>th</SUB> region.</P>