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NEW SOI MATERIALS AND ADVANCED SOI DEVICES
SORIN CRISTOLOVEANU 한국물리학회 2004 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.45 No.2
Recent data on state-of-the-art SOI structures are reported, in order to reveal the key role of the device dimensions: thickness of the buried oxide, gate oxide, and silicon lm. MOSFET miniaturization enables new physics mechanisms. The self-heating problems in SOI MOSFETs can be solved by replacing the buried oxide with a dierent dielectric that oers improved thermal conductivity. The Gate-Induced Floating Body Eects (GIFBE) are described and shown to depend on the device geometry and frequency. In ultra-thin SOI lms, the coupling eects are amplied, leading to interesting consequences for double-gate operation. The operation principles and main features of transistors with 2, 3 or 4 gates are discussed.
Xu, Yue,Cristoloveanu, Sorin,Bawedin, Maryline,Im, Ki-Sik,Lee, Jung-Hee Institute of Electrical and Electronics Engineers 2018 IEEE transactions on electron devices Vol. No.
<P>This paper presents a new concept, supported by 3-D TCAD simulations, for improving the performance and subthreshold swing (SS) of enhancement-mode AlGaN/GaN fin-shaped field-effect transistors (FinFETs). By choosing appropriate device parameters, the formation of 2-D electron gas (2DEG) can be delayed such as to ensure simultaneous activation of 2DEG and sidewall MOS channels at positive threshold voltage for normally off operation. The 2DEG channel starts forming in the middle of the fin, whereas the edges are depleted by the lateral MOS gates. Not only increasing the gate voltage does the 2DEG charge increase, but also the effective width is enlarged being less depleted by the gates. This double-2DEG mechanism adds to the regular MOS channels on the sidewalls and enables enhanced performance. The 3-D TCAD simulations indicate that narrow FinFET (20 nm) can exhibit excellent switching characteristics: very low SS of 55 mV/decade, below the 60 mV/decade limit, high on/off current ratio of 10<SUP>10</SUP>, and good current driving capability due to the added 2DEG channel contribution. The maximum transconductance is 350 mS/mm, the drain current reaches 380 mA/mm, and the on resistance is as low as 0.018 <TEX>$\text{m}\Omega \cdot \text {cm}^{2}$</TEX>.</P>
Comparison for 1/ <tex> ${f}$</tex> Noise Characteristics of AlGaN/GaN FinFET and Planar MISHFET
Vodapally, Sindhuri,Theodorou, Christoforos G.,Bae, Youngho,Ghibaudo, Gerard,Cristoloveanu, Sorin,Im, Ki-Sik,Lee, Jung-Hee IEEE 2017 IEEE transactions on electron devices Vol.64 No.9
<P>DC and 1/f noise performances of the AlGaN/GaN fin-shaped field-effect transistor (FinFET) with fin width of 50 nm were analyzed. The FinFET exhibited approximately six times larger normalized drain current and transconductance, compared to those of the AlGaN/GaN planar metal-insulator-semiconductor heterostructure field-effect-transistor (MISHFET) fabricated on the same wafer. It was also observed that the FinFET exhibited improved noise performance with lower noise magnitude of 8.5x10(-15) A(2)/Hz when compared to the value of 8.7x10(-14)A(2)/Hz for the planar MISHFET. An intensive analysis indicated that both devices follow the carrier number fluctuation model, but the FinFET suffers much less charge trapping effect compared to the MISHFET (two orders lower charge trapping was observed). Moreover, the FinFET did not exhibit the Lorentz-like components, which explains that the depleted fin structure effectively prevents the carriers from being trapped into the underlying thick GaN buffer layer. On the other hand, the slope of the noise is 2 irrespective of drain voltage and apparently showed the Lorentz-like components, especially at high drain voltage in MISHFET device. This explains that the carrier trapping/detrapping between the 2-D electron gas channel and the GaN buffer layer is significant in MISHFET.</P>
Im, Ki-Sik,Kim, Jeong-Gil,Vodapally, Sindhuri,Caulmilone, Raphaë,l,Cristoloveanu, Sorin,Lee, Jung-Hee ELSEVIER 2017 MICROELECTRONIC ENGINEERING Vol.178 No.-
<P><B>Abstract</B></P> <P>The capacitance-voltage (<I>C-V</I>) characterizations of Al<SUB>2</SUB>O<SUB>3</SUB>/GaN-on-insulator (GaNOI) structure, prepared with the Smart Cut™ technology, with and without tetramethylammonium hydroxide (TMAH) surface treatment have been investigated. The GaNOI structure consists of a 150nm-thick GaN layer and a 800μm-thick Si<SUB>3</SUB>N<SUB>4</SUB>/SiO<SUB>2</SUB> buried insulating layer deposited on sapphire substrate. For fabrication of the MIS capacitor, an Al<SUB>2</SUB>O<SUB>3</SUB> layer with thickness of 28nm as a gate dielectric was deposited on the GaNOI wafer by atomic layer deposition (ALD). The calculated carrier concentration of the GaN layer on the buried insulator was increased to 2.8×10<SUP>17</SUP> cm<SUP>−3</SUP> from the value of ~5×10<SUP>16</SUP> cm<SUP>−3</SUP> for the as-grown undoped GaN layer prior to the wafer transfer. The MIS capacitor with TMAH surface treatment showed a positive threshold voltage shift with negligible hysteresis and low interface trap density compared to the capacitor without TMAH surface treatment. Severe frequency dispersion was observed regardless of the TMAH treatment due to the crystal defects generated during the complicated wafer transfer process.</P> <P><B>Highlights</B></P> <P> <UL> <LI> The Al<SUB>2</SUB>O<SUB>3</SUB>/GaN-on-insulator (GaNOI) capacitors were fabricated using TMAH surface treatment. </LI> <LI> The calculated doping density of GaN layer was obtained to 2.8×10<SUP>17</SUP> cm<SUP>−3</SUP>. </LI> <LI> This capacitors exhibited the severe frequency dispersion due to the crystal damaged GaN layer. </LI> <LI> The TMAH surface-treated MIS capacitor showed better performances compared to the TMAH-free device. </LI> </UL> </P> <P><B>Graphical abstract</B></P> <P>[DISPLAY OMISSION]</P>
Growth of AlN/GaN HEMT structure Using Indium-surfactant
Jeong-Gil Kim,Chul-Ho Won,Do-Kywn Kim,Young-Woo Jo,Jun-Hyeok Lee,Yong-Tae Kim,Sorin Cristoloveanu,Jung-Hee Lee 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.5
We have grown AlN/GaN heterostructure which is a promising candidate for mm-wave applications. For the growth of the high quality very thin AlN barrier, indium was introduced as a surfactant at the growth temperature varied from 750 to 1070 ℃, which results in improving electrical properties of two-dimensional electron gas (2DEG). The heterostructure with barrier thickness of 7 ㎚ grown at of 800 ℃ exhibited best Hall measurement results; such as sheet resistance of 215 Ω/□, electron mobility of 1430 ㎠/V·s, and two-dimensional electron gas (2DEG) density of 2.04 x 10<SUP>13</SUP> /㎠. The high electron mobility transistor (HEMT) was fabricated on the grown heterostructure. The device with gate length of 0.2 ㎛ exhibited excellent DC and RF performances; such as maximum drain current of 937 ㎃/㎜, maximum transconductance of 269 mS/㎜, current gain cut-off frequency of 40 ㎓, and maximum oscillation frequency of 80 ㎓.
Gate Architecture Effects on the Gate Leakage Characteristics of GaN Wrap‑gate Nanowire Transistors
Siva Pratap Reddy Mallem,Ki‑Sik Im,Terirama Thingujam,Jung‑Hee Lee,Raphael Caulmilone,Sorin Cristoloveanu 대한금속·재료학회 2020 ELECTRONIC MATERIALS LETTERS Vol.16 No.5
Gate leakage current in lateral GaN wrap-gate nanowire transistors (WG-NWT) was investigated using current density–voltage (Jg–Vg) characteristics at room temperature. We found that the gate leakage current is strongly dependent on thetop corner angle of the gate architecture. This leakage current was characterized by considering hopping (Poole–Frenkelemission) and trap-assisted thermionic emission mechanisms. Despite its smaller gate area, the gate leakage current of thelateral GaN WG-NWT without a 2DEG channel was higher than that of the device with a 2DEG channel for all applied gatebiases. The reason for this is that the lateral GaN WG-NWT without 2DEG channel has a triangular cross-section with asharp top corner angle resulting in a strong electric field due to geometrical field enhancement.
Fabrication of AlGaN/GaN Ω-shaped nanowire fin-shaped FETs by a top-down approach
Im, Ki-Sik,Sindhuri, Vodapally,Jo, Young-Woo,Son, Dong-Hyeok,Lee, Jae-Hoon,Cristoloveanu, Sorin,Lee, Jung-Hee JAPAN SOCIETY OF APPLIED PHYSICS 2015 Applied physics express Vol.8 No.6
<P>An AlGaN/GaN-based Omega-shaped nanowire fin-shaped FET (FinFET) with a fin width of 50 nm was fabricated using tetramethylammonium hydroxide (TMAH)-based lateral wet etching. An atomic layer deposited (ALD) HfO2 side-wall layer served as the etching mask. ALD Al2O3 and TiN layers were used as the gate dielectric and gate metal, respectively. The Omega-shaped gate structure fully depletes the active fin body and almost completely separates the depleted fin from the underlying thick GaN buffer layer, resulting in superior device performance. The top-down processing proposed in this work provides a viable pathway towards gate-all-around devices for III-nitride semiconductors. (C) 2015 The Japan Society of Applied Physics</P>