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S.R. Haldar,A. Nayak,T.K. Chini,S. Bhunia 한국물리학회 2010 Current Applied Physics Vol.10 No.3
We have reported low temperature growth (300 ℃) of ZnO nanorod flower structures by depositing zinc acetate vapor on Ge (100) substrate in the form of a jet using chemical vapor condensation technique. The flowers were comprised of hierarchical arrangement of highly crystalline ZnO nanorods oriented isotropically around a common nucleus. The temperature window for stability of these structures was found to be very narrow and the formation of the flowers was highly depended on the type of the substrates used. The flower morphology changed to a different hemispherical shape when the growth temperature was increased by only 50 ℃ while decreasing the growth temperature of the same degrees resulted in an amorphous deposition of ZnO. The temperature and substrate effect has been explained on the basis of adatom kinetics during growth. X-ray diffraction and TEM study revealed wurtzite ZnO nanorods with lattice constants a and c of 3.2 and 5.19 Å, respectively. The flower structures showed strong room temperature photoluminescence having pure excitonic transition at around 3.298 eV.
Maternal photic regulation of immune status in neonates of Indian palm squirrel Funambulus pennanti
Bishnupuri, K.S.,Haldar, C.,Singh, R. Korean Society of Photoscience 2002 Journal of Photosciences Vol.9 No.2
Till date the phenomenon of maternal transfer of photic information was reported to regulate the fetal/neonatal growth, however its influence on neonatal immune system is still an enigma. In the present study, we observed an increase in maternal plasma melatonin level under short day length (SOL) condition with a consequent decrease in TLC and LC in their respective neonates. However, a significant decrease in maternal plasma melatonin level was noted under constant darkness (DD) with an increase in TLC and LC of their neonates. The blastogenic response (BGR) to Con A of splenocytes exhibited a significant increase in neonates of SDL females and a significant decrease in the neonates of DD females. Hence, it appears that the increase in maternal plasma melatonin under SOL condition transmitted information to decrease the immune status. Continuous exposure of females to darkness (DD) negatively regulated the maternal pineal gland activity thereby decreasing their plasma melatonin level. This information was transmitted for elevation of immune status in neonates, so that they exhibit better growth and sexual maturation. Therefore, we may suggest that the maternal photic information transmitted either prenatally through placenta or postnatally via the milk regulate the hormonal profile of Melatonin to regulate the immune status of neonates in order to influence their growth and sexual maturation.
Ghosh, Pujarini,Haldar, Subhasis,Gupta, R.S.,Gupta, Mridula The Institute of Electronics and Information Engin 2012 Journal of semiconductor technology and science Vol.12 No.4
A Dual metal gate stack cylindrical/ surrounded gate MOSFET (DMGSA CGT/SGT MOSFET) has been proposed and an analytical model has been developed to examine the impact of this structure in suppressing short channel effects and in enhancing the device performance. It is demonstrated that incorporation of gate stack along with dual metal gate architecture results in improvement in short channel immunity. It is also examined that for DMGSA CGT/SGT the minimum surface potential in the channel reduces, resulting increase in electron velocity and thereby improving the carrier transport efficiency. Furthermore, the device has been analyzed at different bias point for both single material gate stack architecture (SMGSA) and dual material gate stack architecture (DMGSA) and found that DMGSA has superior characteristics as compared to SMGSA devices. The analytical results obtained from the proposed model agree well with the simulated results obtained from 3D ATLAS Device simulator.
Ghosh, Pujarini,Haldar, Subhasis,Gupta, R.S.,Gupta, Mridula The Institute of Electronics and Information Engin 2012 Journal of semiconductor technology and science Vol.12 No.4
An intrinsic small signal equivalent circuit model of Cylindrical/Surrounded gate MOSFET is proposed. Admittance parameters of the device are extracted from circuit analysis and intrinsic circuit elements are presented in terms of real and imaginary parts of the admittance parameters. S parameters are then evaluated and justified with the simulated data extracted from 3D device simulation.
Pujarini Ghosh,Subhasis Haldar,R. S. Gupta,Mridula Gupta 대한전자공학회 2012 Journal of semiconductor technology and science Vol.12 No.4
A Dual metal gate stack cylindrical/surrounded gate MOSFET (DMGSA CGT/SGT MOSFET) has been proposed and an analytical model has been developed to examine the impact of this structure in suppressing short channel effects and in enhancing the device performance. It is demonstrated that incorporation of gate stack along with dual metal gate architecture results in improvement in short channel immunity. It is also examined that for DMGSA CGT/SGT the minimum surface potential in the channel reduces, resulting increase in electron velocity and thereby improving the carrier transport efficiency. Furthermore, the device has been analyzed at different bias point for both single material gate stack architecture (SMGSA) and dual material gate stack architecture (DMGSA) and found that DMGSA has superior characteristics as compared to SMGSA devices. The analytical results obtained from the proposed model agree well with the simulated results obtained from 3D ATLAS Device simulator.
Pujarini Ghosh,Subhasis Haldar,R. S. Gupta,Mridula Gupta 대한전자공학회 2012 Journal of semiconductor technology and science Vol.12 No.4
An intrinsic small signal equivalent circuit model of Cylindrical/Surrounded gate MOSFET is proposed. Admittance parameters of the device are extracted from circuit analysis and intrinsic circuit elements are presented in terms of real and imaginary parts of the admittance parameters. S parameters are then evaluated and justified with the simulated data extracted from 3D device simulation.
Mangla, Tina,Sehgal, Amit,Saxena, Manoj,Haldar, Subhasis,Gupta, Mridula,Gupta, R.S. The Institute of Electronics and Information Engin 2005 Journal of semiconductor technology and science Vol.5 No.3
Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and poly-depletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by self-consistent solution of the $Schr{\ddot{o}}dinger$ and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.
Tina Mangla,Amit Sehgal,Manoj Saxena,Subhasis Haldar,Mridula Gupta,R. S. Gupta 대한전자공학회 2005 Journal of semiconductor technology and science Vol.5 No.3
Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and polydepletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by selfconsistent solution of the Schrodinger and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.
Optimization of Gate Stack MOSFETs with Quantization Effects
Mangla, Tina,Sehgal, Amit,Saxena, Manoj,Haldar, Subhasis,Gupta, Mridula,Gupta, R.S. The Institute of Electronics and Information Engin 2004 Journal of semiconductor technology and science Vol.4 No.3
In this paper, an analytical model accounting for the quantum effects in MOSFETs has been developed to study the behaviour of $high-{\kappa}$ dielectrics and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and $I_D-V_D$ characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achieve targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.