http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
Tina Mangla,Amit Sehgal,Manoj Saxena,Subhasis Haldar,Mridula Gupta,R. S. Gupta 대한전자공학회 2005 Journal of semiconductor technology and science Vol.5 No.3
Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and polydepletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by selfconsistent solution of the Schrodinger and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.
Optimization of Gate Stack MOSFETs with Quantization Effects
Mangla, Tina,Sehgal, Amit,Saxena, Manoj,Haldar, Subhasis,Gupta, Mridula,Gupta, R.S. The Institute of Electronics and Information Engin 2004 Journal of semiconductor technology and science Vol.4 No.3
In this paper, an analytical model accounting for the quantum effects in MOSFETs has been developed to study the behaviour of $high-{\kappa}$ dielectrics and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and $I_D-V_D$ characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achieve targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.
Mangla, Tina,Sehgal, Amit,Saxena, Manoj,Haldar, Subhasis,Gupta, Mridula,Gupta, R.S. The Institute of Electronics and Information Engin 2005 Journal of semiconductor technology and science Vol.5 No.3
Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and poly-depletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by self-consistent solution of the $Schr{\ddot{o}}dinger$ and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.
Optimization of Gate Stack MOSFETs with Quantization Effects
Tina Mangla,Amit Sehgal,Manoj Saxena,Subhasis Haldar,Mridula Gupta,R.S.Gupta 대한전자공학회 2004 Journal of semiconductor technology and science Vol.4 No.3
In this paper, an analytical model accounting for the quantum effect. in MOSFETs has been developed to study the behaviour of high-k dielectric. and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and In-Vo characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achie"e targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.<br/> Index Terms-Quantization effects (QEs), Triangular Potential Well (TPW), Gate stack, Equivalent oxide thickness (EOT)<br/>
Poly-crystalline Silicon Thin Film Transistor
Amit Sehgal,Tina Mangla,Mridula Gupta,R. S. Gupta 대한전자공학회 2007 Journal of semiconductor technology and science Vol.7 No.4
A two?dimensional treatment of the potential distribution under the depletion approximation is presented for poly?crystalline silicon thin film transistors. Green’s function approach is adopted to solve the two?dimensional Poisson’s equation. The solution for the potential distribution is derived using Neumann’s boundary condition at the silicon?silicon di?oxide interface. The developed model gives insight into device behavior due to the effects of traps and grain?boundaries. Also short?channel effects and drain induced barrier lowering effects are incorporated in the model. The potential distribution and electric field variation with various device parameters is shown. An analysis of threshold voltage is also presented. The results obtained show good agreement with simulated results and numerical modeling based on the finite difference method, thus demonstrating the validity of our model.
Sehgal, Amit,Mangla, Tina,Gupta, Mridula,Gupta, R.S. The Institute of Electronics and Information Engin 2007 Journal of semiconductor technology and science Vol.7 No.4
A two-dimensional treatment of the potential distribution under the depletion approximation is presented for poly-crystalline silicon thin film transistors. Green's function approach is adopted to solve the two-dimensional Poisson's equation. The solution for the potential distribution is derived using Neumann's boundary condition at the silicon-silicon di-oxide interface. The developed model gives insight into device behavior due to the effects of traps and grain-boundaries. Also short-channel effects and drain induced barrier lowering effects are incorporated in the model. The potential distribution and electric field variation with various device parameters is shown. An analysis of threshold voltage is also presented. The results obtained show good agreement with simulated results and numerical modeling based on the finite difference method, thus demonstrating the validity of our model.