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Shrink Generator-based Strong PUF Architecture with Improved Uniqueness and Reliability on an FPGA
Guard Kanda,Kwangki Ryoo 대한전자공학회 2023 Journal of semiconductor technology and science Vol.23 No.1
Silicon-based Physically Unclonable Functions (PUFs) are a source of physical security primitive that is either implemented on ASICs or FPGAs. A class of these security primitives that provide an exponentially large set of Challenge-Response Pairs (CRPs) is termed Strong PUF. That notwithstanding, the Arbiter and Feedforward Arbiter PUFs which are traditionally Strong PUFs, are not suitable for FPGA implementation. In this paper, a newly proposed PUF architecture that improves on the existing Configurable Ring Oscillator (CRO) PUF by increasing its dynamic configurability and its level of entropy is presented. To maintain the exponentially large set of CRPs, the Shrink Generator is applied to the traditionally Weak CRO-PUF. The proposed design is implemented and tested on a spartan-6 FPGA board using the Xilinx ISE tool. The proposed architecture demonstrates a uniqueness of 50.01% and is 96.43% reliable.
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Run-Time Hardware Trojans Detection Using On-Chip Bus for System-on-Chip Design
박승용,류광기,Kanda, Guard,Park, Seungyong,Ryoo, Kwangki 한국정보통신학회 2016 한국정보통신학회논문지 Vol.20 No.2
본 논문에서는 감염된 IP로부터 악성 공격을 감지하고 예방하기 위한 안전하고 효율적인 온칩버스를 기술한다. 대부분의 상호-연결 시스템(온칩버스)은 모든 데이터와 제어 신호가 밀접하게 연결되어있기 때문에 하드웨어 말웨어 공격에 취약하다. 본 논문에서 제안하는 보안 버스는 개선된 아비터, 어드레스 디코딩, 마스터와 슬레이브 인터페이스로 구성되며, AHB (Advanced High-performance Bus)와 APB(Advance Peripheral Bus)를 이용하여 설계되었다. 또한, 보안 버스는 매 전송마다 아비터가 마스터의 점유율을 확인하고 감염된 마스터와 슬레이브를 관리하는 알고리즘으로 구현하였다. 제안하는 하드웨어는 Xilinx ISE 14.7을 사용하여 설계하였으며, Virtex4 XC4VLX80 FPGA 디바이스가 장착된 HBE-SoC-IPD 테스트 보드를 사용하여 검증하였다. TSMC $0.13{\mu}m$ CMOS 표준 셀 라이브러리로 합성한 결과 약 39K개의 게이트로 구현되었으며 최대 동작주파수는 313MHz이다. A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connects (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 39K at an operating frequency of 313MHz using the $0.13{\mu}m$ TSMC process.
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자원이 제약된 유비쿼터스 장치의 보안을 위한 초경량 LEA 128비트 블록 암호화 아키텍처
안효근,강수동,Kanda Guard,류광기 국제차세대융합기술학회 2022 차세대융합기술학회논문지 Vol.6 No.1
초경량 LEA 128비트 블록 암호화 아키텍처는 자원이 제약된 유비쿼터스 장치에 보안성을 높일 방법으 로, 국가보안기술연구소에서 개발되고 국제표준화기구와 국제전기기술위원회에서 암호 분야 국제 표준으로 제정된 보안 알고리즘인 128비트 Lightweight Encryption Algorithm 알고리즘을 하드웨어 환경에서 설계하여 내부 레지 스터 재사용, 리소스 공유를 통해 LEA 암호화/복호화 모듈을 저 면적으로 구현하였다. Xilinx ISE 14.7 Virtex-5 를 이용하여 합성한 결과, 최대 주파수는 190.88MHz를 달성했으며 최대 128Mbps의 처리 속도를 가진다. 또한, 301개의 Flip-Flop, 1151개의 Look-Up-Table, 485개의 슬라이스로 구현되어 128비트 LEA 알고리즘을 저면적으 로 구현된 하드웨어 디자인을 제시한다. In this paper, we present an efficient hardware design of the 128-bit Lightweight Encryption Algorithm. LEA is a security algorithm developed by the National Security Technology Institute and established as an international standard for cryptography in the International Organization for Standardization and International Electrotechnical Commission for use in a hardware environment. The proposed architecture is based on internal register reuse and resource sharing to lower the LEA encryption/decryption crypto core’s area. The maximum frequency is 190.88MHz and has throughput of 128Mbps. In addition, 301 Flip-Flops, 1151 Look-Up-Tables, and 485 Slices are utilized to present a low-area 128-bit LEA hardware design.
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( Dennis Agyemanh Nana Gookyi ),( Guard Kanda ),( Kwangki Ryoo ) 한국정보처리학회 2021 Journal of information processing systems Vol.17 No.2
In January 2013, the National Institute of Standards and Technology (NIST) announced the CAESAR (Competition for Authenticated Encryption: Security, Applicability, and Robustness) contest to identify authenticated ciphers that are suitable for a wide range of applications. A total of 57 submissions made it into the first round of the competition out of which 6 were announced as winners in March 2019. In the process of the competition, NIST realized that most of the authenticated ciphers submitted were not suitable for resource-constrained devices used as end nodes in the Internet-of-Things (IoT) platform. For that matter, the NIST Lightweight Cryptography Standardization Process was set up to identify authenticated encryption and hashing algorithms for IoT devices. The call for submissions was initiated in 2018 and in April 2019, 56 submissions made it into the first round of the competition. In August 2019, 32 out of the 56 submissions were selected for the second round which is due to end in the year 2021. This work surveys the 32 authenticated encryption schemes that made it into the second round of the NIST lightweight cryptography standardization process. The paper presents an easy-to-understand comparative overview of the recommended parameters, primitives, mode of operation, features, security parameter, and hardware/software performance of the 32 candidate algorithms. The paper goes further by discussing the challenges of the Lightweight Cryptography Standardization Process and provides some suitable recommendations.
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