MgZnSiN_2 : Eu TFEL 소자의 전기, 광학적 특성 Eu TFEL Devices

장지근,임성규,이순석 단국대학교 1998 論文集 Vol.32 No.-

The Mg_xZn_1-xSiN_2:Eu phosphor was studied as a possible material for thin-film electroluminescent (TFEL) device application. Mg, Zn, Si_3N_4, and EuF_3 powders were mixed and fired at 1400℃ to synthesize the Mg_xZn_1-xSiN_2:Eu phosphor. Photoluminescence characteristics of the synthesized phosphors were measured. Electrical characteristics of the Mg_xZn_1-xSiN_2:Eu TFEL devices were also measured.

Si 기판상에 Pt(h00) 박막의 배향성장 연구

장지근,김민영,장호정,김장기 단국대학교 1997 論文集 Vol.31 No.-

Pt thin films with the thickness of about 3000Å have been deposited on the Ti/SiO_2/Si structures in a variety of process conditions by DC magnetron sputtering method followed by the in-situ annealing at 500℃ for 30 minutes and/or the rapid thermal annealing at 650℃ for 20 seconds. As the result of experiments, only the Pt films deposited at room temperature in the atmosphere of Ar showed the [200] preferred orientation after the in-situ annealing regardless to the following rapid thermal annealing The XRD analysis exhibited the orientation rate of 53% with FWHM of 0.6° for the (200) peak in the in-situ annealed sample deposited at room temperature and Ar ambient showing a little increase of the [200]-orientation rate according to the following rapid thermal annealing. From the SEM micrographs, the as-deposited Pt films was observed after post-annealing.

전압 제어형 부성 저항 특성을 갖는 λ 바이폴라 트랜지스터

張志根 단국대학교 1987 論文集 Vol.21 No.-

A three terminal semiconductor device with the characteristics of voltage controlled negative resistance called λ-bipolar transistor is studied experimentally and theoretically. Its structure can be realized by merging N-channel enhancement MOSFET into the base region of integrated npn bipolar transistor. The operation principle and mechanism controlling the differential negative resistance of this device is analyzed and the experimental results are in good agreement with the theory.

고주파 마그네트론 스퍼터링 방법에 의해 MgO(100) 기판위에 증착된 (Pb, La) TiO_3 박막의 제작과 특성연구

張志根,張鎬廷,金敏寧,嚴于鎔 단국대학교 1995 論文集 Vol.29 No.-

Pyroelectric (Pb, La) TiO_3 (PLT) thin films have been prepared on Pt coated MgO(100) substrate by RF magnetron sputtering method in an atmosphere of mixed gas of Ar and O_2. PLT file deposited at 580℃ showed perovskite single phase with prominent C-axis orientation perpendicular to the substrate surface. The full width at half maximum (FWHM) of the PLT film was 0.45 degree indicating good crystallinity. From the RHEED observation, the PLT film showed spotty pattern, indication a single crystal phase with rough film surface. The relative dielectric constant(ε_r) and dielectric loss(tanδ) of the perovskite PLT film deposited at 580℃ were 75 and 0.006 at 1kHz, respectively. From the hysterisis loop analysis using sawyer-tower circuit, the remanent polarization(P_r) and coercive field(E_c) were about 10μC/㎠ and 160kV/㎝, respectively.

바이폴라 집적소자용 Si Photodioded의 설계 및 시물레이션

장지근,이상열,김윤희 단국대학교 신소재기술연구소 2001 신소재 Vol.10 No.-

Optical Link용 receiver module을 one chip IC로 실현하기 위해 바이폴라 집적소자용 si photodiode를 설계하고 simulation기법(tool: SILVACO/ATLAS)을 이용하여 이의 전기·광학적 특성을 분석하였다. 제안된 그물망(web) 모양의 소자는 바이폴라 IC기술로 제작이 가능하며, simulation 결과 에피층의 두께가 12㎛, 도핑정도가 1.1×10^15/㎤인 Si 웨이퍼를 사용할 경우 우수한 디지털 광신호 분리능력{I(1-state_/I(0-state)>10^2}과 약 700nm의 파장 범위에서 peak spectral response를 나타내었다. A Si photodiode was designed and its electro-optical characteristics were analyzed by simulation(tool: SILVACO/ATLAS) to realize one chip received module for optical link. the proposed device can be fabricated by bipolar IC technology. The simulation results show that the web type device has the good discrimination characteristic{1(1-state)/I(0-state)>10^2} between digital optical signals and peak spectral response in the wavelength of about 700 nm when it is fabricated from Si water with epitaxial thickness of 12um and the doping concentration of 1.1×10^15/㎤.

TiO/SiO_2를 이용한 Si FEA 게이트 절연막 연구

장지근,김민영,정진철 단국대학교 신소재기술연구소 2000 신소재 Vol.9 No.-

TiO/SiO_2 이중막을 게이트 절연막으로 이용하여 3극형 Si FEA를 제작하였다. conventional Si FEA 제작에서 TiO/SiO_2 이중막의 사용은 TiO층이 Mo 금속의 접착력을 증가시켜 주므로 BHF용액에서 sharpening oxide를 제거할 때 Mo 금속이 뜨는 현상을 방지할 수 있다. 또한 TiO층은 양호한 절연막의 역할을 수행하면서 BHF 용액에 거의 녹지 않아, 소자제작에서 게이트홀의 과도한 측면인식과 게이트-캐소드간의 누설전류를 줄일 수 있다. The TiO/SiO_2 bilayer as gate insulator was applied in the conventional process of triode-type Si FEA. The application of TiO/SiO_2 bilayer prevents the Mo electrode film on the gate insulator form floating in the BHF solution during the removal of sharpening oxide. This is the result from the improved adhesion between Mo and TiO film. Moreover, TiO film with the property of good insulation is not solulable reduction of the side-etching of gate hole around Si tip and the leakage current between gate and cathode compared to those of the conventional device with the deposited SiO_2.

4-대칭 LMT 구조를 이용한 3차원 반도체 자기센서(Ⅰ) : 제안과 설계 Proposal and Design

장지근,고광렬 단국대학교 신소재기술연구소 1992 신소재 Vol.2 No.-

바이폴라 집적회로 기술에 적합한 4-대칭 LMT(Lateral Magnetotransistor) 구조의 3차원 반도체 자기센서가 설계되고, 소자의 자계감도에 대한 이론적 연구가 실시된다. 설계된 소자는 기본 구조가 산화막 격리, 매몰층, 및 깊은 이미터를 지닌 40대칭 측면 pnp 트랜지스터로 형성되며, 대칭 구조에 따른 우수한 공간을 분해능을 갖는다. 인가된 바이어스 아래, 소자의 4-대칭 컬렉터 쌍의 전류를 분석하면, 3차원 자계 성분을 동시에 결정할 수 있다. 이 논문에서 제안된 새로운 구조의 자기센서가 5㎛ 바이폴라 집적회로 기술을 바탕으로 하여 설계될 때, 공간 분해능이 60×60×5㎛^3로 나타난다. A three-dimensional semiconductor magnetic sensor compatible with bipolar integrated technology is designed using four-symmetrical LMT structures. The device is composed of four-symmetrical lateral pnp transistors with oxide isolation, buried layer, and deep emitter, and has the capability of high spatial resolution due to the symmetrical feature. Under applied bias, analyzing the currents of four-symmetrical collector pairs, we can determine the 3-D magnetic-field components. The magnetic sensor newly proposed in this paper shows the spatial resolution of 60×60×5㎛^3 when it is designed on the basis of 5 ㎛ bipolar technology.

고농도 도핑된 n+-Si 영역상에 Co/Ti 이중막 실리사이드의 형성과 특성연구

장지근,신철상 단국대학교 1999 論文集 Vol.34 No.-

We have studied the formation of Co/Ti bilayer silicide with low resistivity and good thermal stability on the heavily As doped n^+-Si region. In this paper, Co/Ti bilayer silicides were fabricated by depositing Co(150Å)/Ti(50Å) films on the As-implanted n^+-Si region in an E-beam evaporator and performing the two step RTA process (first annealing:650℃/20sec. second annealing:800℃/20sec) in a N_2 ambient with the pressure of 10^-1atm, Co/Ti bilayer silicides obtained from our experiments exhibited the low resistivity of about 19μΩ-㎝ and the uniform thickness of about 500 Å without increase of sheet resistance and occurrence of agglomeration under the long post-annealing time up to 1000℃.

4-대칭 LMT구조를 이용한 3차원 반도체 자기센서(Ⅱ) : 감도특성 Sensitivity

장지근,전병조 단국대학교 신소재기술연구소 1993 신소재 Vol.3 No.-

3차원 자계를 측정할 수 있는 새로운 구조의 4대칭 LMT 반도체 자기센서를 설계하고, 소자의 전·자기적 특성을 이론적으로 모델링하였다. 제안된 소자는 물리적 변수가 X_jc=2.4∼2.6㎛, N_B=10^16cm^-3, X_b=10∼12㎛, L=5∼10㎛로 실현될 때 최적설계가 이루어지며, 소자의 감도특성은 V_CB=10V, B≤0.4[T]에서 S_rxx(S_ryy)≒35[%/T], S_rzz=15[%/T]로 나타났다. 최적 설계인 4대칭 LMT 소자는 종래의 3차원 반도체 자기센서에 비해 넓은 자계범위에서 높은 채널상대감도 특성을 나타내며, 114×114×5㎛^3의 미소 공간분해능으로 5[T]까지의 자계크기를 감지할 수 있다. We have designed a new semiconductor device capable of measuring 3-D magnetic field using four symmetrical LMT structures. This device can be optimally designed when physical parameters are as follows: a depth of collector is in a range of (2.4∼∼2.6)㎛ and a length/doping concentration of the base is in a range of (10∼12)㎛/10^15cm^-3, and a distance between collector pairs is in a range of (5∼10)㎛, respectively. The optimally designed magnetic sensor has a spatial resolution of(114×114×5)㎛^3 and exhibits a sensitivity characteristics of S_rxx(S_ryy)≒35[%/T] in the x(y)-channel and S_rzz≒15[%/T] in the z-channel under the condition of V_CB=10V, B≤0.4[T]. This device shows a good performance in the electromagnetic characteristics with little of cross-sensitivities in comparison to other devices reported so far having an upper measuring limit of approximately 5[T].

高低接合 에미터 構造를 갖는 N^+ NPP^+ Si 太陽電池의 效率改善

張志根 단국대학교 1984 論文集 Vol.18 No.-

N^+NPP^+ HLEBSF(high low emitter back surface field) solar cells which have N^+N high low junction in the emitter as well as N^+PP^+ BSF cells were designed and fabricated by using <111> oriented P type Si wafers with the resistivity of 10Ω-㎝ and the thickness of 13∼15mil. Physical parameters (impurity concentration, thickness) at each region of N^+PP^+ and N^+NPP^+ cell were made equally through same masks and simultaneous process except N region of HLEBSF cell to investigate the high low emitter junction effect for efficiency improvement. Under the light intensity of 100㎽/㎠, total area (active area) conversion efficiency were typically 10.94%(12.16%) for N^+PP^+ BSF cells and 12.07%(13.41%) for N^+NPP^+ cells, Efficiency improvement of N^+NPP^+ cell which has high low emitter junction structure is resulted from the suppression of emitter recombination current and the increasement of open circuit voltage(V_(oc))and short circuit current(I_(sh)) by removing heavy doping effects occurring in N^+ emitter region.