일제강점기 주택의 응접실에 관한 연구 - 《朝鮮と建築》의 주택 사례를 중심으로

박채린(Park, Chaerin),이경아(Lee, Kyung-Ah) 대한건축학회 2021 대한건축학회논문집 Vol.37 No.10

This study examined how Western-style housing culture was accepted and changed in Korea through the analysis of the reception room of houses during the Japanese colonial period. The reception room was a typical Western-style space, with carpets on the floor, imported wallpaper and curtains on the walls, Western-style furniture and a fireplace. It was made not only as a public space for welcoming guests, but also as a conspicuous space and a space for appreciation of a house owner. However, due to the circumstances of the Japanese colonial period, Japanese and Korean elements such as Dadami, Dokonoma and Ondol were mixed in the Western-style reception room. As time passed, the size of the reception room became smaller or combined with other rooms, and the decorations decreased, and it is now a space that can no longer be found in Korea.

1950~80년대 한반도 비무장지대 안 대성동마을에 관한 연구

박채린(Park, Chaerin),이경아(Lee, Kyung-Ah) 대한건축학회 2022 대한건축학회논문집 Vol.38 No.1

This study examines the transition process of Daeseong-dong Village located in the Demilitarized Zone on the Korean Peninsula from the 1950s to the 1980s and reinterprets the meaning of the formation of Daeseong-dong Village, which has been known only as a village for propaganda against North Korea. Daeseong-dong Village was developed three times in 1959, 1971~1972, and 1979~1983, with new layout plans being implemented for each development, and new types of houses being built, transforming it into a village specialized in propaganda against North Korea. In particular, the first comprehensive development project of Daeseong-dong Village became an ideal village in general rural areas in Korea in the early 1970s as a demonstration village of the Saemaul Movement. In addition, Daeseong-dong Village played a role as a demonstration village of a Unification Village(Tongilchon) established in a special area called a Civilian Control Zone located in the border regions.

건축자산 진흥 시행계획의 수립현황과 특성

박채린(Park, Chaerin),이규철(Lee, Geau-Chul) 대한건축학회 2022 대한건축학회 학술발표대회 논문집 Vol.42 No.2

국외사적지 활용·관리를 위한 공유유산 개념 적용 방안 연구

박채린(Park, Chaerin),손은신(Son, Eun-Shin) 대한건축학회 2023 대한건축학회 학술발표대회 논문집 Vol.43 No.2

This study aims to derive the direction of applying the concept of shared heritage for the preservation, utilization, and management of Korean overseas historic sites and the criteria for target selection. Shared heritage is a heritage in which two or more countries share the historical and cultural values of the cultural property. This study analyzes the main status and types of Korean overseas historic sites based on the existing survey list, and derived priority criteria for exclusion and selection of shared heritage through the process of deriving the main provisional list of K-shared heritage.

벤처기업의 전략적 제휴에서 파트너특성, 제휴유형, 지배구조의 경영성과에 대한 효과

박종훈,윤채린 한국중소기업학회 2003 中小企業硏究 Vol.25 No.2

본 연구는 전략적 제휴를 수립하려는 벤처기업이 어떤 특성의 파트너기업을 선택하고 이들과 어떤 형태의 제휴와 어떤 방식으로 지배구조를 설계하는 것이 벤처기업의 성과 제고에 효과적인지를 분석하고자 한다. 이와 같은 연구목적을 달성하기 위해 코스닥에 상장된 78개의 벤처기업들이 추진한 153건의 전략적 제휴를 대상으로 실증분석하였다. 벤처기업들이 추진한 제휴를 분석한 결과 벤처기업이 상대적으로 더 큰 규모의 파트너와 전략적 제휴를 수립할수록 기업성과가 향상되는 것으로 나타났다. 또한 파트너의 상대적 규모가 가져오는 효과가 제휴의 유형에 따라 달라지는지를 고찰해본 결과 시장제휴와 기술제휴에 따라 그 효과에 있어서 유의한 차이가 존재하지 않는 것으로 나타났다. 마지막으로 제휴에 있어서 지분공유의 효과를 분석해 본 결과, 파트너의 상대적 규모가 가져오는 효과가 파트너의 지분공유가 낮을 때는 유의하게 나타났지만, 파트너의 지분공유가 높을 때는 그 효과가 약화되는 것으로 나타났다. 따라서, 본 연구는 전략적 제휴에서 파트너기업과의 관계특성에 따른 기업성과에서의 효과가 모든 상황에서 동일하게 나타나는 것이 아니라 파트너의 특성을 고려하여 지배구조가 적절하게 설계될 때 나타난다는 것을 시사한다. The purpose of this study is to examine the effects of partner characteristics, alliance type and alliance governance structure on the performance of venture firms entering strategic alliances. More specifically, this study hypothesizes relationships among relative partner size, alliance type, degree of equity sharing and venture firms' performance, and tests them based on a sample of 153 alliances formed by 78 Korean venture firms during the period of 1999-2001. It is found that the performance of venture firms tends to be greater when they formed alliances with larger firms. It is also found that the positive effects of relative partner size on firm performance are not significantly different between marketing alliances and technology alliances. However, the positive effect of relative parter size is found to be moderated by the degree of partners' equity sharing: that is, the positive effect decreases as the degree of partners' equity sharing increases. These results suggest that venture firms can enhance performance gains when they carefully combine partner characteristics, alliance type, and the governance structure of strategic alliance.

A 4-Channel 6.25-Gb/s/ch VCSEL Driver for HDMI 2.0 Active Optical Cables

Chaerin Hong,Sung Min Park 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.4

This paper presents a 4-channel common-cathode VCSEL driver array operating up to 6.25 Gb/s per channel for the applications of HDMI 2.0 active optical cables. The proposed VCSEL driver consists of an input buffer, a modified Cherry-Hooper amplifier as a pre-driver, and a main driver with pre-emphasis to drive a common-cathode VCSEL diode at high-speed full switching operations. Particularly, the input buffer merges a linear equalizer not only to broaden the bandwidth, but to reduce power consumption simultaneously. Measured results of the proposed 4-channel VCSEL driver array implemented in a 0.13-μm CMOS process demonstrate wide and clean eye-diagrams for up to 6.25-Gb/s operation speed with the bias current 2.0 mA and the modulation currents of 3.1 mAPP. Chip core occupies the area of 0.15 x 0.1 μm² and dissipate 22.8 mW per channel.

A 4-Channel 6.25-Gb/s/ch VCSEL Driver for HDMI 2.0 Active Optical Cables

Hong, Chaerin,Park, Sung Min The Institute of Electronics and Information Engin 2017 Journal of semiconductor technology and science Vol.17 No.4

This paper presents a 4-channel common-cathode VCSEL driver array operating up to 6.25 Gb/s per channel for the applications of HDMI 2.0 active optical cables. The proposed VCSEL driver consists of an input buffer, a modified Cherry-Hooper amplifier as a pre-driver, and a main driver with pre-emphasis to drive a common-cathode VCSEL diode at high-speed full switching operations. Particularly, the input buffer merges a linear equalizer not only to broaden the bandwidth, but to reduce power consumption simultaneously. Measured results of the proposed 4-channel VCSEL driver array implemented in a $0.13-{\mu}m$ CMOS process demonstrate wide and clean eye-diagrams for up to 6.25-Gb/s operation speed with the bias current 2.0 mA and the modulation currents of $3.1mA_{PP}$. Chip core occupies the area of $0.15{\times}0.1{\mu}m^2$ and dissipate 22.8 mW per channel.

10-미터 HDMI 2.1 POF 액티브 광케이블용 4x10-Gb/s/ch 트랜시버 칩셋

홍채린(Chaerin Hong),박성민(Sung Min Park) 대한전자공학회 2018 대한전자공학회 학술대회 Vol.2018 No.6

무인차량 라이다용 CMOS 듀얼채널 자동 이득조절 트랜스임피던스 증폭기 어레이

홍채린(Chaerin Hong),박성민(Sung Min Park) 대한전기학회 2016 전기학회논문지 Vol.65 No.5

In this paper, a dual-channel feed-forward transimpedance(TIA) array is realized in a standard 0.18-μm CMOS technology which exploits automatic gain control function to provide 40-dB input dynamic range for either detecting targets nearby or sensing imminent danger situations. Compared to the previously reported conventional feed-forward TIA, the proposed automatic-gain-control feed-forward TIA(AFF-TIA) extends the input dynamic range 25 dB wider by employing a 4-level automatic gain control circuit. Measured results demonstrate the linearly varying transimpedance gain of 47 to 72 dBΩ, input dynamic range of 1:100, the bandwidth of ≧670 MHz, the equivalent input referred noise current spectral density of 6.9 pA/√HZ, the maximum sensitivity of –26.8 dBm for 10<SUP>-12</SUP> BER, and the power consumption of 27.6 mW from a single 1.8-V supply. The dual-channel chip occupies the area of 1.0 × 0.73 ㎟ including I/O pads.

4-채널 3.125-Gb/s/ch VCSEL 드라이버 어레이

홍채린(Chaerin Hong),박성민(Sung Min Park) 대한전자공학회 2017 전자공학회논문지 Vol.54 No.1

본 논문에서는 채널 당 3.125-Gb/s 동작 속도를 갖는 4-채널 공통-캐소드 VCSEL 다이오드 드라이버 어레이 칩을 구현하였다. 스위칭 동작하는 메인 드라이버의 동작속도 향상을 위해, 액티브 인덕터를 사용한 전치증폭단과 이퀄라이저 기능을 탑재한 입력버퍼단으로 구성하였다. 특히 개선된 입력버퍼단의 경우, 주파수 영역의 피킹으로 대역폭 증대뿐 아니라 비교적 적은 전류로 동작하도록 설계하였다. 본 논문에서 사용한 VCSEL 다이오드는 2.2 V 순방향 전압과 50 Ω 기생저항 및 850 fF 기생 캐패시턴스를 갖는다. 또한, 3.0 mA 변조전류 및 3.3 mA 바이어스 전류로 동작하므로, 두 개의 독립적인 전류소스로 구동 가능한 current steering 기반의 메인 드라이버를 설계하였다. 제안한 4-채널 광 송신기 어레이 칩은 0.11-μm CMOS 공정을 이용하여 제작하였다. 칩 코어의 면적은 0.15×0.18 μ㎡ 이며, 채널 당 22.3 mW 전력소모를 갖는다. In this paper, a 4-channel common-cathode VCSEL diode driver array with 3.125 Gb/s per channel operation speed is realized. In order to achieve faster speed of the switching main driver with relatively large transistors, the transmitter array chip consists of a pre-amplifier with active inductor stage and also an input buffer with modified equalizer, which leads to bandwidth extension and reduced current consumption. The utilized VCSEL diode provides inherently 2.2 V forward bias voltage, 50 Ω resistance, and 850 fF capacitance. In addition, the main driver based upon current steering technique is designed, so that two individual current sources can provide bias currents of 3.0 mA and modulation currents of 3.3 mA to VCSEL diodes. The proposed 4-channel VCSEL driver array has been implemented by using a 0.11-μm CMOS technology, and the chip core occupies the area of 0.15×0.18 μ㎡ and dissipates 22.3 mW per channel.