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RISS 인기검색어
- 검색키워드
- 저자 : A.N. Ragheb (검색결과 6 건)
- 무료
- 기관 내 무료
- 유료
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Ragheb, A.N.,Kim, HyungWon,Lee, Jae-Jin Elsevier 2018 Microelectronics Journal Vol.79 No.-
<P>This paper introduces an energy-efficient dynamic voltage scaler (DVS) based on charge- pump and binary-weighted capacitor digital to analog converter (BWC-DAC). Conventional DVS architectures suffer from long settling-time beside the limitation of coarse voltage resolution, so we propose DVS architecture based on BWC-DAC architecture. It takes advantage of DAC's reconfigurable structure to provide an output voltage scaled with high resolution of V-IN/2(N) for input voltage VIN and N configuration bits; and Nano-second transition time. However, DAC inherently suffers from low power efficiency because it requires frequent reset to maintain the output voltage. To overcome this issue, a high efficiency charge-pump is employed to restore the charges in DAC's capacitors without the need to reset which results in improved power efficiency. The proposed DVS with a 6-bit DAC and a feedback controlled circuit have been implemented using a 130 nm CMOS process. The measurement results show an accurate 64 voltage levels of the 6-bit DAC from 0 V to 1.476 V, when supplied by an input voltage of 1.5 V. We achieved a peak efficiency of 84% for load current ranging from 1 mu A-14.76 mu A. Furthermore, it provides an extremely short settling time that is as short as 83.6 Nano second.</P>
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Low-Power Voltage Converter Using Energy Recycling Capacitor Array
Shah, Syed Asmat Ali,Ragheb, A.N.,Kim, HyungWon The Korea Institute of Information and Commucation 2017 Journal of information and communication convergen Vol.15 No.1
This paper presents a low-power voltage converter based on a reconfigurable capacitor array. Its energy recycling capacitor array stores the energy during a charge stage and supplies the voltage during an energy recycle stage even after the power source is disconnected. The converter reconfigures the capacitor array step-wise to boost the lost voltage level during the energy recycle stage. Its energy saving is particularly effective when most of the energy remaining in the charge capacitors is wasted by the leakage current during a longer sleep period. Simulations have been conducted using a voltage source of 500 mV to supply a $V_{DD}$ of around 800 mV to a load circuit consisting of four 32-bit adders in a 65-nm CMOS process. Results demonstrate energy recycling efficiency of 85.86% and overall energy saving of 40.14% compared to a conventional converter, when the load circuit is shortly active followed by a long sleep period.
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A. N. Ragheb,강호진,박경한,원동민,김형원 한국과학기술원 반도체설계교육센터 2016 IDEC Journal of Integrated Circuits and Systems Vol.2 No.1
This paper proposes an efficient method to improve the performance of the projected mutual capacitance large touch screen panels (TSPs) based on differential offset cancellation technique. To achieve high scan rate the proposed architecture uses concurrent and continuous sine waves as driving technique. In contrast to the conventional offset compensation topologies cannot handle such a concurrent or continuous signals properly, however, the proposed architecture overcomes such switching noise. In addition to, it provides an effective noise cancellation for such signals. The proposed architecture has been implemented using a Magnachip/SK Hynix 0.18 µm CMOS process. However, the measured results show a 14 dB improvement I SNR compared to conventional architectures. Also, the proposed readout circuit shows a good performance after mismatch condition applied to input stage of the differential amplifier to show the effectiveness of the proposed cancellation technique.
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Ultra low power wide-band mixer circuit based on subthreshold operation for MB-OFDM UWB
Ragheb, A.N.,Kim, H. Mackintosh Publications] 2016 Microelectronics Journal Vol.50 No.-
<P>This paper presents an extremely low power down-conversion mixer based on subthreshold operation for MB-OFDM UWB receiver, for the first band of operation 3.1-3.628 GHz. The proposed down conversion mixer uses a double balanced Gilbert cell to provide the required performance in the conversion gain (CG) and the isolation among ports. It includes an input matching network (IMN) to enhance the input matching of the mixer. The proposed mixer is designed such that all transistors work in subthreshold regime under a supply voltage of 0.5 V, thus resulting in extremely low power consumption. We implemented the proposed mixer using a 0.18 mu m CMOS process. Simulation experiments show that the conversion gain of the mixer is 2.17-3.25 dB over the frequency range of 3.1-3.628 GHz when IF port is terminated with 50 Omega. The noise figure of the mixer is 5.12-5.93 dB, while the LO-IF isolation is lower than 111 dB. The 1-dB compression point is -16.68 dBm, third-order input intercept point IIP3 is -5.7 dBm. The experiments show that the proposed design consumes only 6.6 uW at 0.5 V, which is extremely low power compared with existing work. (C) 2016 Elsevier Ltd. All rights reserved.</P>
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Dynamic Voltage Scaler Based on Binary-Weighted Charge Redistribution Digital-to-Analog Converter
Kyeong-Han Park(박경한),A. N. Ragheb,Hyung-Won Kim(김형원) 대한전자공학회 2016 대한전자공학회 학술대회 Vol.2016 No.6
This paper presents a dynamic voltage scaler architecture based on binary-weighted charge redistributed digital-to-analog (DAC) converter. The proposed architecture uses a DAC as a reconfigurable voltage scaler based on digital control circuit to select the required voltage level. Whereas it is difficult for the conventional voltage converters to scale the output voltage, the output voltage of the proposed architecture can be accurately scaled by the resolution of DAC. The proposed voltage scaler using a 3-bit DAC has been implemented using a 65nm CMOS process. The simulation results with the 3-bit DAC showed accurate 8 output voltage levels of 0 V to 1.05 V from an input voltage of 1.2V. When the proposed voltage scaler was configured to supply 600mV to a 32-bit adder, it showed a small ripple voltage of 10 mV and consumed energy of 4.425 pJ for 6 addition operations during the simulation of 780 nsec.
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Energy Recycling Voltage Scaler Based on Reconfigurable Capacitive Array
Syed Asmat Ali Shah,A.N. Ragheb,HyungWon Kim(김형원) 대한전자공학회 2016 대한전자공학회 학술대회 Vol.2016 No.6
This paper introduces a novel architecture of voltage scaler based on a reconfigurable capacitive array. While its reconfigurable structure allows it to scale the output voltage to any target level, its energy recycling process permits the voltage scaler to supply the voltage even after the input voltage is turned off. This architecture stores the energy in the capacitor array during the voltage scaling stage, then it reconfigures these charges step-wise to boost the lost voltage level during the energy recycling stage. Using the proposed architecture, an example voltage scaler was implemented using 65 nm CMOS process, which generates an output voltage of a range 500 mV to 1.16 V from an input voltage of 500 mV. Simulations were conducted with a 32-bit adder circuit as a load, which showed a reduction in energy consumption by 45.8% compared to a conventional converter.
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